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| author | michael-west <michael.west@ettus.com> | 2015-04-08 18:04:47 -0700 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2015-04-10 18:32:59 -0700 |
| commit | f23e7bcc47f86ffb431aee43abe670e3e5e31647 (patch) | |
| tree | a3a58267a6e0b091db59f0a9c3bcd666e50f5a67 | |
| parent | b0d87e24f90e291a6940a6cba89bf2c2ebcb971e (diff) | |
| download | uhd-f23e7bcc47f86ffb431aee43abe670e3e5e31647.tar.gz uhd-f23e7bcc47f86ffb431aee43abe670e3e5e31647.tar.bz2 uhd-f23e7bcc47f86ffb431aee43abe670e3e5e31647.zip | |
Increase command FIFO depth of N2x0 and X3x0 to 64.
| -rw-r--r-- | host/lib/usrp/usrp2/fw_common.h | 2 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_fifo_ctrl.cpp | 2 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.hpp | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h index 337a1ad6f..cfaee0ddc 100644 --- a/host/lib/usrp/usrp2/fw_common.h +++ b/host/lib/usrp/usrp2/fw_common.h @@ -30,7 +30,7 @@ extern "C" { #endif //fpga and firmware compatibility numbers -#define USRP2_FPGA_COMPAT_NUM 10 +#define USRP2_FPGA_COMPAT_NUM 11 #define USRP2_FW_COMPAT_NUM 12 #define USRP2_FW_VER_MINOR 4 diff --git a/host/lib/usrp/usrp2/usrp2_fifo_ctrl.cpp b/host/lib/usrp/usrp2/usrp2_fifo_ctrl.cpp index 0276a7a66..e0544862d 100644 --- a/host/lib/usrp/usrp2/usrp2_fifo_ctrl.cpp +++ b/host/lib/usrp/usrp2/usrp2_fifo_ctrl.cpp @@ -33,7 +33,7 @@ static const size_t POKE32_CMD = (1 << 8); static const size_t PEEK32_CMD = 0; static const double ACK_TIMEOUT = 0.5; static const double MASSIVE_TIMEOUT = 10.0; //for when we wait on a timed command -static const boost::uint32_t MAX_SEQS_OUT = 15; +static const boost::uint32_t MAX_SEQS_OUT = 63; #define SPI_DIV SR_SPI_CORE + 0 #define SPI_CTRL SR_SPI_CORE + 1 diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp index 342664ece..890ef7bcb 100644 --- a/host/lib/usrp/x300/x300_impl.hpp +++ b/host/lib/usrp/x300/x300_impl.hpp @@ -70,13 +70,13 @@ static const size_t X300_PCIE_RX_DATA_FRAME_SIZE = 8184; //bytes static const size_t X300_PCIE_TX_DATA_FRAME_SIZE = 8192; //bytes static const size_t X300_PCIE_DATA_NUM_FRAMES = 2048; static const size_t X300_PCIE_MSG_FRAME_SIZE = 256; //bytes -static const size_t X300_PCIE_MSG_NUM_FRAMES = 32; +static const size_t X300_PCIE_MSG_NUM_FRAMES = 64; static const size_t X300_10GE_DATA_FRAME_MAX_SIZE = 8000; //bytes static const size_t X300_1GE_DATA_FRAME_MAX_SIZE = 1472; //bytes static const size_t X300_ETH_MSG_FRAME_SIZE = uhd::transport::udp_simple::mtu; //bytes -static const size_t X300_ETH_MSG_NUM_FRAMES = 32; +static const size_t X300_ETH_MSG_NUM_FRAMES = 64; static const size_t X300_ETH_DATA_NUM_FRAMES = 32; static const double X300_DEFAULT_SYSREF_RATE = 10e6; |