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authorMatt Ettus <matt@ettus.com>2010-07-16 16:16:45 -0700
committerMatt Ettus <matt@ettus.com>2010-07-16 16:16:45 -0700
commited0679e33f7405e33816b7d6a4dce80a54a5cf40 (patch)
treedfe613451b4b02676680966b6287a82bdfa941df
parentcc1a35023361784adb05f1159c3ba8f5ececc6a5 (diff)
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remove warnings
-rw-r--r--usrp2/sdr_lib/dsp_core_tx.v4
-rw-r--r--usrp2/vrt/vita_tx_deframer.v2
2 files changed, 3 insertions, 3 deletions
diff --git a/usrp2/sdr_lib/dsp_core_tx.v b/usrp2/sdr_lib/dsp_core_tx.v
index 22d3d44a3..79d92c9b3 100644
--- a/usrp2/sdr_lib/dsp_core_tx.v
+++ b/usrp2/sdr_lib/dsp_core_tx.v
@@ -29,11 +29,11 @@ module dsp_core_tx
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({scale_i,scale_q}),.changed());
- setting_reg #(.my_addr(BASE+2)) sr_2
+ setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed());
- setting_reg #(.my_addr(BASE+4)) sr_4
+ setting_reg #(.my_addr(BASE+4), .width(8)) sr_4
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({dacmux_b,dacmux_a}),.changed());
diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v
index 220d3b061..3b95f5902 100644
--- a/usrp2/vrt/vita_tx_deframer.v
+++ b/usrp2/vrt/vita_tx_deframer.v
@@ -22,7 +22,7 @@ module vita_tx_deframer
);
wire [1:0] numchan;
- setting_reg #(.my_addr(BASE), .at_reset(0)) sr_numchan
+ setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(numchan),.changed());