move the streamid so it isn't at the same address as clear_state

2 files changed, 2 insertions, 2 deletions

diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v
index 04ec5abe8..92bf13ff9 100644
--- a/usrp2/fifo/fifo36_mux.v
+++ b/usrp2/fifo/fifo36_mux.v
@@ -52,6 +52,6 @@ module fifo36_mux
    assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0;
    assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0;
    assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0;
-   assign data_0 = (state==MUX_DATA0) ? data0_i : data1_i;
+   assign data_o = (state==MUX_DATA0) ? data0_i : data1_i;
    
 endmodule // fifo36_demux
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index cc091f2d5..84e502b5f 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -21,7 +21,7 @@ module vita_tx_chain
    wire [31:0] 	  streamid, message;
    wire 	  trigger, sent;
    
-   setting_reg #(.my_addr(BASE_CTRL+1), .at_reset(0)) sr_streamid
+   setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(streamid),.changed());