Merge branch 'master' into ashish/cat_refactor_phase2

20 files changed, 95 insertions, 132 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 6a7856e9a..75067b3b2 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@ Change Log for Releases
 ==============================
 
 ## 003.007.002
+* Fixed X300 phase alignment issues
+* Fixed CMake 2.6 incompatibility issues
+* EEPROM burner improvements
 * Properly flushing PCIe chain on device to prevent stale data.
 * Adjusted bus clock rate in FPGA to improve timing.
 * Fixed issue where FPGA would fail to load FPGA image over PCIe.
diff --git a/fpga/usrp3/top/x300/Makefile.x300.inc b/fpga/usrp3/top/x300/Makefile.x300.inc
index 1395b5f00..6e13e4fed 100644
--- a/fpga/usrp3/top/x300/Makefile.x300.inc
+++ b/fpga/usrp3/top/x300/Makefile.x300.inc
@@ -49,7 +49,7 @@ synthesis_tool "XST (VHDL/Verilog)" \
 simulator "ISim (VHDL/Verilog)" \
 "Preferred Language" "Verilog" \
 "Enable Message Filtering" FALSE \
-"Display Incremental Messages" FALSE 
+"Display Incremental Messages" FALSE
 
 ##################################################
 # Sources
@@ -142,7 +142,8 @@ MAP_PROPERTIES = \
 "Map Effort Level" High \
 "Extra Effort" Normal \
 "Perform Timing-Driven Packing and Placement" TRUE \
-"Enable Multi-Threading 2"
+"Enable Multi-Threading 2" \
+"Starting Placer Cost Table (1-100)" $$(( $$RANDOM % 100 + 1 ))
 #"Map to Input Functions" 4 \
 
 PLACE_ROUTE_PROPERTIES = \
@@ -160,6 +161,6 @@ GEN_PROG_FILE_PROPERTIES = \
 "Done (Output Events)" 5 \
 "Enable Bitstream Compression" FALSE \
 "Enable Outputs (Output Events)" 6 \
-"Wait for DCI Match (Output Events)" NoWait 
+"Wait for DCI Match (Output Events)" NoWait
 
 SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp3/top/x300/bus_int.v b/fpga/usrp3/top/x300/bus_int.v
index 416b327bb..38991dad6 100644
--- a/fpga/usrp3/top/x300/bus_int.v
+++ b/fpga/usrp3/top/x300/bus_int.v
@@ -141,7 +141,7 @@ module bus_int
    localparam RB_BIST         = 8'd128;
 
 
-   localparam COMPAT_MAJOR    = 16'h0006;
+   localparam COMPAT_MAJOR    = 16'h0007;
    localparam COMPAT_MINOR    = 16'h0000;
 
    wire [31:0] 	  set_data;
diff --git a/fpga/usrp3/top/x300/capture_ddrlvds.v b/fpga/usrp3/top/x300/capture_ddrlvds.v
index 193caf6e1..308171fc7 100644
--- a/fpga/usrp3/top/x300/capture_ddrlvds.v
+++ b/fpga/usrp3/top/x300/capture_ddrlvds.v
@@ -1,25 +1,26 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2014 Ettus Research LLC
 //
 
-
-
+// The two clocks are aligned externally in order to eliminate the need for a FIFO.
+// A FIFO cannot be used to transition between clock domains because it can cause
+// alignment issues between the output of multiple modules.
 
 module capture_ddrlvds
   #(parameter WIDTH=7,
     parameter X300=0)
    (input clk,
-    input reset,
     input ssclk_p,
     input ssclk_n,
     input [WIDTH-1:0] in_p,
     input [WIDTH-1:0] in_n,
-    output [(2*WIDTH)-1:0] out);
+    output reg [(2*WIDTH)-1:0] out);
 
    wire [WIDTH-1:0] 	   ddr_dat;
    wire 		   ssclk;
    wire [(2*WIDTH)-1:0]    out_pre1;
-   wire 		   ssclk_bufio1, ssclk_bufio2, ssclk_bufr, ssclk_bufmr;
+   reg  [(2*WIDTH)-1:0]    out_pre2;
+   wire 		   ssclk_bufio1, ssclk_bufio2, ssclk_bufmr;
 
    IBUFGDS #(.DIFF_TERM("TRUE"))
    clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
@@ -33,20 +34,12 @@ module capture_ddrlvds
 		    .I(ssclk_bufmr),
 		    .O(ssclk_bufio1)
 		   );
+
    BUFIO clkbufio2 (
 		    .I(ssclk_bufmr),
 		    .O(ssclk_bufio2)
 		    );
 
-   BUFR
-     #(.SIM_DEVICE("7SERIES"),
-       .BUFR_DIVIDE("BYPASS"))
-   clkbufr (
-	    .I(ssclk_bufmr),
-	    .O(ssclk_bufr)
-	    );
-
-
    genvar 		   i;
 
    generate
@@ -68,34 +61,7 @@ module capture_ddrlvds
 	end
    endgenerate
 
-
-
-   reg rd_en;
-   wire full, empty, almost_empty;
-
-
-   input_sample_fifo  input_sample_fifo_i
-     (
-      .rst(reset), // input rst
-      .wr_clk(ssclk_bufr), // input wr_clk
-      .rd_clk(clk), // input rd_clk
-      .din(out_pre1), // input [27 : 0] din
-      .wr_en(1'b1), // input wr_en
-      .rd_en(rd_en), // input rd_en
-      .dout(out), // output [27 : 0] dout
-      .full(full), // output full
-      .empty(empty), // output empty
-      .almost_empty(almost_empty) // output almost_empty
-      );
-
-
-   always @(posedge clk) begin
-      if (reset)
-	rd_en <= 0;
-      else if (~almost_empty)
-	rd_en <= 1;
-      else if (empty)
-	rd_en <= 0;
-   end
+   always @(posedge clk)
+     {out, out_pre2} <= {out_pre2, out_pre1};
 
 endmodule // capture_ddrlvds
diff --git a/fpga/usrp3/top/x300/timing.ucf b/fpga/usrp3/top/x300/timing.ucf
index a84a92a63..b638b2c99 100644
--- a/fpga/usrp3/top/x300/timing.ucf
+++ b/fpga/usrp3/top/x300/timing.ucf
@@ -34,3 +34,8 @@ TIMESPEC TS_IOPORT2_CLK_TO_BUS_CLK_FALEPATH = FROM ioport2_clk_grp TO bus_clk_gr
 TIMESPEC TS_IOPORT2_CLK_TO_RIO40_CLK_FALEPATH = FROM ioport2_clk_grp TO rio40_clk_grp TIG;
 TIMESPEC TS_RIO40_CLK_TO_IOPORT2_CLK_FALEPATH = FROM rio40_clk_grp TO ioport2_clk_grp TIG;
 
+# FPGA_CLK_p/n is externally phase shifted to allow for crossing from the ADC clock domain
+# to the radio_clk (aka FPGA_CLK_p/n) clock domain. To ensure this timing is consistent,
+# lock the locations of the MMCM and BUFG to generate radio_clk.
+INST "radio_clk_gen/mmcm_adv_inst" LOC = MMCME2_ADV_X0Y0;
+INST "radio_clk_gen/clkout1_buf" LOC = BUFGCTRL_X0Y8;
\ No newline at end of file
diff --git a/fpga/usrp3/top/x300/x300.v b/fpga/usrp3/top/x300/x300.v
index e9191a481..e57ae7b3b 100644
--- a/fpga/usrp3/top/x300/x300.v
+++ b/fpga/usrp3/top/x300/x300.v
@@ -484,7 +484,7 @@ module x300
    //  so I gets a double negative, and is unchanged.  Q must be inverted.
 
    capture_ddrlvds #(.WIDTH(14),.X300(1)) cap_db0
-     (.clk(radio_clk), .reset(radio_rst), .ssclk_p(DB0_ADC_DCLK_P), .ssclk_n(DB0_ADC_DCLK_N),
+     (.clk(radio_clk), .ssclk_p(DB0_ADC_DCLK_P), .ssclk_n(DB0_ADC_DCLK_N),
       .in_p({{DB0_ADC_DA6_P, DB0_ADC_DA5_P, DB0_ADC_DA4_P, DB0_ADC_DA3_P, DB0_ADC_DA2_P, DB0_ADC_DA1_P, DB0_ADC_DA0_P},
          {DB0_ADC_DB6_P, DB0_ADC_DB5_P, DB0_ADC_DB4_P, DB0_ADC_DB3_P, DB0_ADC_DB2_P, DB0_ADC_DB1_P, DB0_ADC_DB0_P}}),
 
@@ -494,7 +494,7 @@ module x300
    assign rx0[31:0] = { rx0_i, 2'b00, ~rx0_q_inv, 2'b00 };
 
    capture_ddrlvds #(.WIDTH(14),.X300(1)) cap_db1
-     (.clk(radio_clk),  .reset(radio_rst), .ssclk_p(DB1_ADC_DCLK_P), .ssclk_n(DB1_ADC_DCLK_N),
+     (.clk(radio_clk), .ssclk_p(DB1_ADC_DCLK_P), .ssclk_n(DB1_ADC_DCLK_N),
       .in_p({{DB1_ADC_DA6_P, DB1_ADC_DA5_P, DB1_ADC_DA4_P, DB1_ADC_DA3_P, DB1_ADC_DA2_P, DB1_ADC_DA1_P, DB1_ADC_DA0_P},
          {DB1_ADC_DB6_P, DB1_ADC_DB5_P, DB1_ADC_DB4_P, DB1_ADC_DB3_P, DB1_ADC_DB2_P, DB1_ADC_DB1_P, DB1_ADC_DB0_P}}),
 
diff --git a/host/CMakeLists.txt b/host/CMakeLists.txt
index 89797d26a..82bcbb30a 100644
--- a/host/CMakeLists.txt
+++ b/host/CMakeLists.txt
@@ -149,7 +149,7 @@ IF(MSVC)
     IF(BOOST_ALL_DYN_LINK)
         ADD_DEFINITIONS(-DBOOST_ALL_DYN_LINK) #setup boost auto-linking in msvc
     ELSE(BOOST_ALL_DYN_LINK)
-        UNSET(BOOST_REQUIRED_COMPONENTS) #empty components list for static link
+        SET(BOOST_REQUIRED_COMPONENTS) #empty components list for static link
     ENDIF(BOOST_ALL_DYN_LINK)
 ENDIF(MSVC)
 
@@ -262,8 +262,8 @@ STRING(REPLACE ";" " " UHD_PC_LIBS "${UHD_PC_LIBS}")
 
 #unset these vars to avoid hard-coded paths to cross environment
 IF(CMAKE_CROSSCOMPILING)
-    UNSET(UHD_PC_CFLAGS)
-    UNSET(UHD_PC_LIBS)
+    SET(UHD_PC_CFLAGS)
+    SET(UHD_PC_LIBS)
 ENDIF(CMAKE_CROSSCOMPILING)
 
 IF(NOT LIBUHD_PKG AND NOT UHDHOST_PKG)
diff --git a/host/cmake/Modules/FindORC.cmake b/host/cmake/Modules/FindORC.cmake
index 0d9fc9ca1..e13eae235 100644
--- a/host/cmake/Modules/FindORC.cmake
+++ b/host/cmake/Modules/FindORC.cmake
@@ -9,7 +9,7 @@ PKG_CHECK_MODULES(PC_ORC_V4_11 "orc-0.4 > 0.4.11")
 #we are using the pkg config as a version check
 #if we have pkg config, the right version must be found
 #the alternative is that no pkg config orc is found
-if (PC_ORC_V4_11_FOUND OR (NOT PC_ORC_FOUND AND NOT PC_ORC_V4_11_FOUND))
+if (PC_ORC_V4_11_FOUND OR NOT PC_ORC_FOUND)
 
 FIND_PATH(
     ORC_INCLUDE_DIRS
diff --git a/host/cmake/Modules/FindUSB1.cmake b/host/cmake/Modules/FindUSB1.cmake
index 96e2a5aae..1e8e3ba03 100644
--- a/host/cmake/Modules/FindUSB1.cmake
+++ b/host/cmake/Modules/FindUSB1.cmake
@@ -23,7 +23,7 @@ FIND_PATH(LIBUSB_INCLUDE_DIRS
 set(libusb1_library_names usb-1.0 libusb-1.0)
 
 #libusb-1.0 compatible library on freebsd
-if((CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") OR (CMAKE_SYSTEM_NAME STREQUAL "kFreeBSD"))
+if(CMAKE_SYSTEM_NAME STREQUAL "FreeBSD" OR CMAKE_SYSTEM_NAME STREQUAL "kFreeBSD")
     list(APPEND libusb1_library_names usb)
 endif()
 
diff --git a/host/cmake/Modules/UHDPackage.cmake b/host/cmake/Modules/UHDPackage.cmake
index d1c0fc099..a050a083d 100644
--- a/host/cmake/Modules/UHDPackage.cmake
+++ b/host/cmake/Modules/UHDPackage.cmake
@@ -63,22 +63,24 @@ ELSEIF(DEBIAN AND LIBUHDDEV_PKG)
 ELSEIF(DEBIAN AND UHDHOST_PKG)
     SET(CPACK_PACKAGE_FILE_NAME "uhd-host_${TRIMMED_UHD_VERSION}_${CMAKE_SYSTEM_PROCESSOR}")
 ELSE()
-    FIND_PROGRAM(LSB_RELEASE_EXECUTABLE lsb_release)
-    IF((DEBIAN OR REDHAT) AND LSB_RELEASE_EXECUTABLE)
-
-        #extract system information by executing the commands
-        EXECUTE_PROCESS(
-            COMMAND ${LSB_RELEASE_EXECUTABLE} --short --id
-            OUTPUT_VARIABLE LSB_ID OUTPUT_STRIP_TRAILING_WHITESPACE
-        )
-        EXECUTE_PROCESS(
-            COMMAND ${LSB_RELEASE_EXECUTABLE} --short --release
-            OUTPUT_VARIABLE LSB_RELEASE OUTPUT_STRIP_TRAILING_WHITESPACE
-        )
-
-        #set a more sensible package name for this system
-        SET(CPACK_PACKAGE_FILE_NAME "uhd_${UHD_VERSION}_${LSB_ID}-${LSB_RELEASE}-${CMAKE_SYSTEM_PROCESSOR}")
-ENDIF()
+    IF(DEBIAN OR REDHAT)
+        FIND_PROGRAM(LSB_RELEASE_EXECUTABLE lsb_release)
+
+        IF(LSB_RELEASE_EXECUTABLE)
+            #extract system information by executing the commands
+            EXECUTE_PROCESS(
+                COMMAND ${LSB_RELEASE_EXECUTABLE} --short --id
+                OUTPUT_VARIABLE LSB_ID OUTPUT_STRIP_TRAILING_WHITESPACE
+            )
+            EXECUTE_PROCESS(
+                COMMAND ${LSB_RELEASE_EXECUTABLE} --short --release
+                OUTPUT_VARIABLE LSB_RELEASE OUTPUT_STRIP_TRAILING_WHITESPACE
+            )
+
+            #set a more sensible package name for this system
+            SET(CPACK_PACKAGE_FILE_NAME "uhd_${UHD_VERSION}_${LSB_ID}-${LSB_RELEASE}-${CMAKE_SYSTEM_PROCESSOR}")
+        ENDIF(LSB_RELEASE_EXECUTABLE)
+    ENDIF(DEBIAN OR REDHAT)
 ENDIF(DEBIAN AND LIBUHD_PKG)
 
 IF(${CPACK_GENERATOR} STREQUAL NSIS)
diff --git a/host/lib/convert/CMakeLists.txt b/host/lib/convert/CMakeLists.txt
index 473b7f59f..363555f45 100644
--- a/host/lib/convert/CMakeLists.txt
+++ b/host/lib/convert/CMakeLists.txt
@@ -66,7 +66,7 @@ ENDIF()
 
 SET(CMAKE_REQUIRED_FLAGS ${EMMINTRIN_FLAGS})
 CHECK_INCLUDE_FILE_CXX(emmintrin.h HAVE_EMMINTRIN_H)
-UNSET(CMAKE_REQUIRED_FLAGS)
+SET(CMAKE_REQUIRED_FLAGS)
 
 IF(HAVE_EMMINTRIN_H)
     SET(convert_with_sse2_sources
diff --git a/host/lib/ic_reg_maps/CMakeLists.txt b/host/lib/ic_reg_maps/CMakeLists.txt
index 889c725db..c810c04ad 100644
--- a/host/lib/ic_reg_maps/CMakeLists.txt
+++ b/host/lib/ic_reg_maps/CMakeLists.txt
@@ -117,4 +117,4 @@ LIBUHD_PYTHON_GEN_SOURCE(
     ${CMAKE_CURRENT_BINARY_DIR}/lmk04816_regs.hpp
 )
 
-UNSET(LIBUHD_PYTHON_GEN_SOURCE_DEPS)
+SET(LIBUHD_PYTHON_GEN_SOURCE_DEPS)
diff --git a/host/lib/types/CMakeLists.txt b/host/lib/types/CMakeLists.txt
index 7fc6bdd94..f19043c1e 100644
--- a/host/lib/types/CMakeLists.txt
+++ b/host/lib/types/CMakeLists.txt
@@ -31,7 +31,7 @@ CHECK_CXX_SOURCE_COMPILES("
     }
     " HAVE_CLOCK_GETTIME
 )
-UNSET(CMAKE_REQUIRED_LIBRARIES)
+SET(CMAKE_REQUIRED_LIBRARIES)
 
 INCLUDE(CheckCXXSourceCompiles)
 CHECK_CXX_SOURCE_COMPILES("
diff --git a/host/lib/usrp/b200/b200_impl.cpp b/host/lib/usrp/b200/b200_impl.cpp
index f33f6ef2c..5c9324cb9 100644
--- a/host/lib/usrp/b200/b200_impl.cpp
+++ b/host/lib/usrp/b200/b200_impl.cpp
@@ -502,11 +502,6 @@ b200_impl::b200_impl(const device_addr_t &device_addr)
         UHD_MSG(status) << "Initializing time to the internal GPSDO" << std::endl;
         const time_t tp = time_t(_gps->get_sensor("gps_time").to_int()+1);
         _tree->access<time_spec_t>(mb_path / "time" / "pps").set(time_spec_t(tp));
-
-        //wait for next PPS edge (timeout after 1 second)
-        time_spec_t pps_time = _tree->access<time_spec_t>(mb_path / "time" / "pps").get();
-        for (size_t i = 0; i < 10 && _tree->access<time_spec_t>(mb_path / "time" / "pps").get() == pps_time; i++)
-            boost::this_thread::sleep(boost::posix_time::milliseconds(100));
     } else {
         //init to internal clock and time source
         _tree->access<std::string>(mb_path / "clock_source/value").set("internal");
diff --git a/host/lib/usrp/multi_usrp.cpp b/host/lib/usrp/multi_usrp.cpp
index 7d19fcb8b..388cf03fa 100644
--- a/host/lib/usrp/multi_usrp.cpp
+++ b/host/lib/usrp/multi_usrp.cpp
@@ -394,17 +394,19 @@ public:
 
     void set_time_unknown_pps(const time_spec_t &time_spec){
         UHD_MSG(status) << "    1) catch time transition at pps edge" << std::endl;
-        time_spec_t time_start = get_time_now();
+        boost::system_time end_time = boost::get_system_time() + boost::posix_time::milliseconds(1100);
         time_spec_t time_start_last_pps = get_time_last_pps();
-        while(true){
-            if (get_time_last_pps() != time_start_last_pps) break;
-            if ((get_time_now() - time_start) > time_spec_t(1.1)){
+        while (time_start_last_pps == get_time_last_pps())
+        {
+            if (boost::get_system_time() > end_time)
+            {
                 throw uhd::runtime_error(
                     "Board 0 may not be getting a PPS signal!\n"
                     "No PPS detected within the time interval.\n"
                     "See the application notes for your device.\n"
                 );
             }
+            boost::this_thread::sleep(boost::posix_time::milliseconds(1));
         }
 
         UHD_MSG(status) << "    2) set times next pps (synchronously)" << std::endl;
diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp
index 2ad15aade..93885fbd3 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.cpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.cpp
@@ -764,11 +764,6 @@ usrp2_impl::usrp2_impl(const device_addr_t &_device_addr){
             UHD_MSG(status) << "Initializing time to the internal GPSDO" << std::endl;
             const time_t tp = time_t(_mbc[mb].gps->get_sensor("gps_time").to_int()+1);
             _tree->access<time_spec_t>(root / "time" / "pps").set(time_spec_t(tp));
-
-            //wait for next PPS edge (timeout after 1 second)
-            time_spec_t pps_time = _tree->access<time_spec_t>(root / "time" / "pps").get();
-            for (size_t i = 0; i < 10 && _tree->access<time_spec_t>(root / "time" / "pps").get() == pps_time; i++)
-                boost::this_thread::sleep(boost::posix_time::milliseconds(100));
         }
     }
 
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp
index a8b30a0ab..da97dd2cf 100644
--- a/host/lib/usrp/x300/x300_clock_ctrl.cpp
+++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp
@@ -283,6 +283,7 @@ void set_master_clock_rate(double clock_rate) {
     _lmk04816_regs.CLKout0_1_PD = lmk04816_regs_t::CLKOUT0_1_PD_POWER_UP;
     this->write_regs(0);
     _lmk04816_regs.CLKout0_1_DIV = vco_div;
+    _lmk04816_regs.CLKout0_ADLY_SEL = lmk04816_regs_t::CLKOUT0_ADLY_SEL_D_EV_X;
     this->write_regs(0);
 
     // Register 1
@@ -294,6 +295,8 @@ void set_master_clock_rate(double clock_rate) {
     // Register 3
     _lmk04816_regs.CLKout6_7_DIV = vco_div;
     _lmk04816_regs.CLKout6_7_OSCin_Sel = lmk04816_regs_t::CLKOUT6_7_OSCIN_SEL_VCO;
+    _lmk04816_regs.CLKout6_ADLY_SEL = lmk04816_regs_t::CLKOUT6_ADLY_SEL_D_EV_X;
+    _lmk04816_regs.CLKout7_ADLY_SEL = lmk04816_regs_t::CLKOUT7_ADLY_SEL_D_EV_X;
     // Register 4
     _lmk04816_regs.CLKout8_9_DIV = vco_div;
     // Register 5
@@ -305,12 +308,20 @@ void set_master_clock_rate(double clock_rate) {
     _lmk04816_regs.CLKout1_TYPE = lmk04816_regs_t::CLKOUT1_TYPE_P_DOWN; //CPRI feedback clock, use LVDS
     _lmk04816_regs.CLKout2_TYPE = lmk04816_regs_t::CLKOUT2_TYPE_LVPECL_700MVPP; //DB_0_RX
     _lmk04816_regs.CLKout3_TYPE = lmk04816_regs_t::CLKOUT3_TYPE_LVPECL_700MVPP; //DB_1_RX
+    // Analog delay of 900ps to synchronize the radio clock with the source synchronous ADC clocks.
+    // This delay may need to vary due to temperature.  Tested and verified at room temperature only.
+    _lmk04816_regs.CLKout0_1_ADLY = 0x10;
+
     // Register 7
     _lmk04816_regs.CLKout4_TYPE = lmk04816_regs_t::CLKOUT4_TYPE_LVPECL_700MVPP; //DB_1_TX
     _lmk04816_regs.CLKout5_TYPE = lmk04816_regs_t::CLKOUT5_TYPE_LVPECL_700MVPP; //DB_0_TX
     _lmk04816_regs.CLKout6_TYPE = lmk04816_regs_t::CLKOUT6_TYPE_LVPECL_700MVPP; //DB0_DAC
     _lmk04816_regs.CLKout7_TYPE = lmk04816_regs_t::CLKOUT7_TYPE_LVPECL_700MVPP; //DB1_DAC
     _lmk04816_regs.CLKout8_TYPE = lmk04816_regs_t::CLKOUT8_TYPE_LVPECL_700MVPP; //DB0_ADC
+    // Analog delay of 900ps to synchronize the DAC reference clocks with the source synchronous DAC clocks.
+    // This delay may need to vary due to temperature.  Tested and verified at room temperature only.
+    _lmk04816_regs.CLKout6_7_ADLY = 0x10;
+
     // Register 8
     _lmk04816_regs.CLKout9_TYPE = lmk04816_regs_t::CLKOUT9_TYPE_LVPECL_700MVPP; //DB1_ADC
     _lmk04816_regs.CLKout10_TYPE = lmk04816_regs_t::CLKOUT10_TYPE_LVDS; //REF_CLKOUT
diff --git a/host/lib/usrp/x300/x300_fw_common.h b/host/lib/usrp/x300/x300_fw_common.h
index 0bbaee319..f1ff5ce7d 100644
--- a/host/lib/usrp/x300/x300_fw_common.h
+++ b/host/lib/usrp/x300/x300_fw_common.h
@@ -31,7 +31,7 @@ extern "C" {
 
 #define X300_FW_COMPAT_MAJOR 3
 #define X300_FW_COMPAT_MINOR 0
-#define X300_FPGA_COMPAT_MAJOR 6
+#define X300_FPGA_COMPAT_MAJOR 7
 
 //shared memory sections - in between the stack and the program space
 #define X300_FW_SHMEM_BASE 0x6000
diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp
index 365828679..d5eacc3ea 100644
--- a/host/lib/usrp/x300/x300_impl.cpp
+++ b/host/lib/usrp/x300/x300_impl.cpp
@@ -810,45 +810,32 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
     _tree->access<subdev_spec_t>(mb_path / "tx_subdev_spec").set(tx_fe_spec);
 
     UHD_MSG(status) << "Initializing clock and PPS references..." << std::endl;
-    try {
-        //First, try external source
-        _tree->access<std::string>(mb_path / "clock_source" / "value").set("external");
-        wait_for_ref_locked(mb.zpu_ctrl, 1.0);
-        _tree->access<std::string>(mb_path / "time_source" / "value").set("external");
-        UHD_MSG(status) << "References initialized to external sources" << std::endl;
-    } catch (uhd::exception::runtime_error &e) {
-        //No external source detected - set to the GPSDO if installed
-        if (mb.gps and mb.gps->gps_detected())
-        {
-            _tree->access<std::string>(mb_path / "clock_source" / "value").set("gpsdo");
-            try {
-                wait_for_ref_locked(mb.zpu_ctrl, 1.0);
-            } catch (uhd::exception::runtime_error &e) {
-                UHD_MSG(warning) << "Clock reference failed to lock to GPSDO during device initialization.  " <<
-                    "Check for the lock before operation or ignore this warning if using another clock source." << std::endl;
-            }
-            _tree->access<std::string>(mb_path / "time_source" / "value").set("gpsdo");
-            UHD_MSG(status) << "References initialized to GPSDO sources" << std::endl;
-            UHD_MSG(status) << "Initializing time to the GPSDO time" << std::endl;
-            const time_t tp = time_t(mb.gps->get_sensor("gps_time").to_int()+1);
-            _tree->access<time_spec_t>(mb_path / "time" / "pps").set(time_spec_t(tp));
-
-            //wait for next PPS edge (timeout after 1 second)
-            time_spec_t pps_time = _tree->access<time_spec_t>(mb_path / "time" / "pps").get();
-            for (size_t i = 0; i < 10 && _tree->access<time_spec_t>(mb_path / "time" / "pps").get() == pps_time; i++)
-                boost::this_thread::sleep(boost::posix_time::milliseconds(100));
-        } else {
-            _tree->access<std::string>(mb_path / "clock_source" / "value").set("internal");
-            try {
-                wait_for_ref_locked(mb.zpu_ctrl, 1.0);
-            } catch (uhd::exception::runtime_error &e) {
-                // Ignore for now - It can sometimes take longer than 1 second to lock and that is OK.
-                //UHD_MSG(warning) << "Clock reference failed to lock to internal source during device initialization.  " <<
-                //    "Check for the lock before operation or ignore this warning if using another clock source." << std::endl;
-            }
-            _tree->access<std::string>(mb_path / "time_source" / "value").set("internal");
-            UHD_MSG(status) << "References initialized to internal sources" << std::endl;
+    //Set to the GPSDO if installed
+    if (mb.gps and mb.gps->gps_detected())
+    {
+        _tree->access<std::string>(mb_path / "clock_source" / "value").set("gpsdo");
+        try {
+            wait_for_ref_locked(mb.zpu_ctrl, 1.0);
+        } catch (uhd::exception::runtime_error &e) {
+            UHD_MSG(warning) << "Clock reference failed to lock to GPSDO during device initialization.  " <<
+                "Check for the lock before operation or ignore this warning if using another clock source." << std::endl;
+        }
+        _tree->access<std::string>(mb_path / "time_source" / "value").set("gpsdo");
+        UHD_MSG(status) << "References initialized to GPSDO sources" << std::endl;
+        UHD_MSG(status) << "Initializing time to the GPSDO time" << std::endl;
+        const time_t tp = time_t(mb.gps->get_sensor("gps_time").to_int()+1);
+        _tree->access<time_spec_t>(mb_path / "time" / "pps").set(time_spec_t(tp));
+    } else {
+        _tree->access<std::string>(mb_path / "clock_source" / "value").set("internal");
+        try {
+            wait_for_ref_locked(mb.zpu_ctrl, 1.0);
+        } catch (uhd::exception::runtime_error &e) {
+            // Ignore for now - It can sometimes take longer than 1 second to lock and that is OK.
+            //UHD_MSG(warning) << "Clock reference failed to lock to internal source during device initialization.  " <<
+            //    "Check for the lock before operation or ignore this warning if using another clock source." << std::endl;
         }
+        _tree->access<std::string>(mb_path / "time_source" / "value").set("internal");
+        UHD_MSG(status) << "References initialized to internal sources" << std::endl;
     }
 }
 
@@ -1396,10 +1383,6 @@ void x300_impl::update_clock_source(mboard_members_t &mb, const std::string &sou
 
     this->update_clock_control(mb);
 
-    //reset the clock control
-    //without this, the lock time is long and can be as much as 30 seconds
-    mb.clock->reset_clocks();
-
     /* FIXME:  implement when we know the correct timeouts
      * //wait for lock
      * double timeout = 1.0;
diff --git a/host/lib/utils/CMakeLists.txt b/host/lib/utils/CMakeLists.txt
index 2252f3221..106e2b650 100644
--- a/host/lib/utils/CMakeLists.txt
+++ b/host/lib/utils/CMakeLists.txt
@@ -84,7 +84,7 @@ CHECK_CXX_SOURCE_COMPILES("
     }
     " HAVE_DLOPEN
 )
-UNSET(CMAKE_REQUIRED_LIBRARIES)
+SET(CMAKE_REQUIRED_LIBRARIES)
 
 CHECK_CXX_SOURCE_COMPILES("
     #define WIN32_LEAN_AND_MEAN