Merge branch 'e110_support'

4 files changed, 130 insertions, 13 deletions

diff --git a/fpga/usrp2/top/E1x0/Makefile b/fpga/usrp2/top/E1x0/Makefile.E100
index 19fb93ebf..9b9a48911 100644
--- a/fpga/usrp2/top/E1x0/Makefile
+++ b/fpga/usrp2/top/E1x0/Makefile.E100
@@ -6,7 +6,7 @@
 # Project Setup
 ##################################################
 TOP_MODULE = u1e
-BUILD_DIR = $(abspath build$(ISE))
+BUILD_DIR = $(abspath build$(ISE)-E100)
 
 ##################################################
 # Include other makefiles
diff --git a/fpga/usrp2/top/E1x0/Makefile.E110 b/fpga/usrp2/top/E1x0/Makefile.E110
new file mode 100644
index 000000000..be2761baf
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/Makefile.E110
@@ -0,0 +1,101 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u1e
+BUILD_DIR = $(abspath build$(ISE)-E110)
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../gpmc/Makefile.srcs
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd3400a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u1e_core.v \
+u1e.v \
+u1e.ucf \
+timing.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPMC_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf
index f94685438..47c250c2f 100644
--- a/fpga/usrp2/top/E1x0/timing.ucf
+++ b/fpga/usrp2/top/E1x0/timing.ucf
@@ -6,18 +6,18 @@ NET "EM_CLK" TNM_NET = "EM_CLK";
 TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 12048 ps HIGH 50 %;
 
 #constrain GPMC IO
-NET "EM_D<*>" MAXDELAY = 5 ns;
-NET "EM_A<*>" MAXDELAY = 5 ns;
-NET "EM_NBE<*>" MAXDELAY = 5 ns;
-NET "EM_NCS4" MAXDELAY = 5 ns;
-NET "EM_NCS6" MAXDELAY = 5 ns;
-NET "EM_NWE" MAXDELAY = 5 ns;
-NET "EM_NOE" MAXDELAY = 5 ns;
+NET "EM_D<*>" MAXDELAY = 5.5 ns;
+NET "EM_A<*>" MAXDELAY = 5.5 ns;
+NET "EM_NBE<*>" MAXDELAY = 5.5 ns;
+NET "EM_NCS4" MAXDELAY = 5.5 ns;
+NET "EM_NCS6" MAXDELAY = 5.5 ns;
+NET "EM_NWE" MAXDELAY = 5.5 ns;
+NET "EM_NOE" MAXDELAY = 5.5 ns;
 
 #constrain interrupt lines
-NET "overo_gpio144" MAXDELAY = 5 ns; #have space
-NET "overo_gpio146" MAXDELAY = 5 ns; #have data
-NET "overo_gpio147" MAXDELAY = 5 ns; #have msg/aux spi miso
+NET "overo_gpio144" MAXDELAY = 5.5 ns; #have space
+NET "overo_gpio146" MAXDELAY = 5.5 ns; #have data
+NET "overo_gpio147" MAXDELAY = 5.5 ns; #have msg/aux spi miso
 
 #NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
 #NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
diff --git a/images/Makefile b/images/Makefile
index b8361addc..284fc302a 100644
--- a/images/Makefile
+++ b/images/Makefile
@@ -248,13 +248,29 @@ _usrp_e100_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_e100_fpga_v2.bin
 IMAGES_LIST += $(_usrp_e100_fpga_bin)
 
 $(_usrp_e100_fpga_bin): $(GLOBAL_DEPS)
-	cd $(_usrp_e100_fpga_dir) && make clean
-	cd $(_usrp_e100_fpga_dir) && make bin
+	cd $(_usrp_e100_fpga_dir) && make -f Makefile.E100 clean
+	cd $(_usrp_e100_fpga_dir) && make -f Makefile.E100 bin
 	cp $(_usrp_e100_fpga_dir)/build/u1e.bin $@
 
 endif
 
 ########################################################################
+# USRP-E110 fpga
+########################################################################
+ifdef HAS_XTCLSH
+
+_usrp_e110_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/E1x0
+_usrp_e110_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_e110_fpga.bin
+IMAGES_LIST += $(_usrp_e110_fpga_bin)
+
+$(_usrp_e110_fpga_bin): $(GLOBAL_DEPS)
+	cd $(_usrp_e110_fpga_dir) && make -f Makefile.E110 clean
+	cd $(_usrp_e110_fpga_dir) && make -f Makefile.E110 bin
+	cp $(_usrp_e110_fpga_dir)/build/u1e.bin $@
+
+endif
+
+########################################################################
 # Build rules
 ########################################################################
 images: $(IMAGES_LIST)