x300: Addressed code review feedback for Rev7+ support

4 files changed, 137 insertions, 129 deletions

diff --git a/host/lib/usrp/mboard_eeprom.cpp b/host/lib/usrp/mboard_eeprom.cpp
index c2415763b..f60182c76 100644
--- a/host/lib/usrp/mboard_eeprom.cpp
+++ b/host/lib/usrp/mboard_eeprom.cpp
@@ -240,16 +240,16 @@ static void load_x300(mboard_eeprom_t &mb_eeprom, i2c_iface &iface)
         iface.read_eeprom(X300_EEPROM_ADDR, offsetof(x300_eeprom_map, revision), 2)
     );
 
-    //extract the product code
-    mb_eeprom["product"] = uint16_bytes_to_string(
-        iface.read_eeprom(X300_EEPROM_ADDR, offsetof(x300_eeprom_map, product), 2)
-    );
-
     //extract the revision compat number
     mb_eeprom["revision_compat"] = uint16_bytes_to_string(
         iface.read_eeprom(X300_EEPROM_ADDR, offsetof(x300_eeprom_map, revision_compat), 2)
     );
 
+    //extract the product code
+    mb_eeprom["product"] = uint16_bytes_to_string(
+        iface.read_eeprom(X300_EEPROM_ADDR, offsetof(x300_eeprom_map, product), 2)
+    );
+
     //extract the mac addresses
     mb_eeprom["mac-addr0"] = mac_addr_t::from_bytes(iface.read_eeprom(
         X300_EEPROM_ADDR, offsetof(x300_eeprom_map, mac_addr0), 6
@@ -291,18 +291,18 @@ static void store_x300(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface)
         string_to_uint16_bytes(mb_eeprom["revision"])
     );
 
-    //parse the product code
-    if (mb_eeprom.has_key("product")) iface.write_eeprom(
-        X300_EEPROM_ADDR, offsetof(x300_eeprom_map, product),
-        string_to_uint16_bytes(mb_eeprom["product"])
-    );
-
     //parse the revision compat number
     if (mb_eeprom.has_key("revision_compat")) iface.write_eeprom(
         X300_EEPROM_ADDR, offsetof(x300_eeprom_map, revision_compat),
         string_to_uint16_bytes(mb_eeprom["revision_compat"])
     );
 
+    //parse the product code
+    if (mb_eeprom.has_key("product")) iface.write_eeprom(
+        X300_EEPROM_ADDR, offsetof(x300_eeprom_map, product),
+        string_to_uint16_bytes(mb_eeprom["product"])
+    );
+
     //store the mac addresses
     if (mb_eeprom.has_key("mac-addr0")) iface.write_eeprom(
         X300_EEPROM_ADDR, offsetof(x300_eeprom_map, mac_addr0),
diff --git a/host/lib/usrp/x300/x300_fw_common.h b/host/lib/usrp/x300/x300_fw_common.h
index 79b6670b3..63dbd1d32 100644
--- a/host/lib/usrp/x300/x300_fw_common.h
+++ b/host/lib/usrp/x300/x300_fw_common.h
@@ -30,6 +30,7 @@ extern "C" {
 #endif
 
 #define X300_REVISION_COMPAT 7
+#define X300_REVISION_MIN    2
 #define X300_FW_COMPAT_MAJOR 4
 #define X300_FW_COMPAT_MINOR 0
 #define X300_FPGA_COMPAT_MAJOR 11
diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp
index f466d3bf5..c742d34df 100644
--- a/host/lib/usrp/x300/x300_impl.cpp
+++ b/host/lib/usrp/x300/x300_impl.cpp
@@ -562,7 +562,7 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
     bool recover_mb_eeprom = dev_addr.has_key("recover_mb_eeprom");
     if (recover_mb_eeprom) {
         UHD_MSG(warning) << "UHD is operating in EEPROM Recovery Mode which disables hardware version "
-                            "checks. Operating in this mode may cause hardware damage and unstable "
+                            "checks.\nOperating in this mode may cause hardware damage and unstable "
                             "radio performance!"<< std::endl;
     }
 
@@ -580,7 +580,7 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
         default:
             if (not recover_mb_eeprom)
                 throw uhd::runtime_error("Unrecognized product type.\n"
-                                         "Either the software does not support this device in which case please update UHD/NI-USRP to the latest version and retry OR\n"
+                                         "Either the software does not support this device in which case please update your driver software to the latest version and retry OR\n"
                                          "The product code in the EEPROM is corrupt and may require reprogramming.");
     }
     _tree->create<std::string>(mb_path / "name").set(product_name);
@@ -625,30 +625,37 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
         }
     } else {
         if (not recover_mb_eeprom)
-            throw uhd::runtime_error("No revision detected MB EEPROM must be reprogrammed!");
+            throw uhd::runtime_error("No revision detected. MB EEPROM must be reprogrammed!");
     }
 
-    if (mb_eeprom.has_key("revision_compat") and not mb_eeprom["revision_compat"].empty()) {
-        size_t hw_rev_compat = 0;
-        try {
-            hw_rev_compat = boost::lexical_cast<size_t>(mb_eeprom["revision_compat"]);
-        } catch(...) {
+    size_t hw_rev_compat = 0;
+    if (mb.hw_rev >= 7) { //Revision compat was added with revision 7
+        if (mb_eeprom.has_key("revision_compat") and not mb_eeprom["revision_compat"].empty()) {
+            try {
+                hw_rev_compat = boost::lexical_cast<size_t>(mb_eeprom["revision_compat"]);
+            } catch(...) {
+                if (not recover_mb_eeprom)
+                    throw uhd::runtime_error("Revision compat in EEPROM is invalid! Please reprogram your EEPROM.");
+            }
+        } else {
             if (not recover_mb_eeprom)
-                throw uhd::runtime_error("Revision compat in EEPROM is invalid! Please reprogram your EEPROM.");
+                throw uhd::runtime_error("No revision compat detected. MB EEPROM must be reprogrammed!");
         }
+    } else {
+        //For older HW just assume that revision_compat = revision
+        hw_rev_compat = mb.hw_rev;
+    }
 
-        if (hw_rev_compat > X300_REVISION_COMPAT) {
+    if (hw_rev_compat > X300_REVISION_COMPAT) {
+        if (not recover_mb_eeprom)
             throw uhd::runtime_error(str(boost::format(
-                "Hardware is too new for this software. Please upgrade to a UHD/NI-USRP that supports hardware revision %d.")
+                "Hardware is too new for this software. Please upgrade to a driver that supports hardware revision %d.")
                 % mb.hw_rev));
-        } else if (hw_rev_compat < X300_REVISION_COMPAT) {
+    } else if (mb.hw_rev < X300_REVISION_MIN) { //Compare min against the revision (and not compat) to give us more leeway for partial support for a compat
+        if (not recover_mb_eeprom)
             throw uhd::runtime_error(str(boost::format(
-                "Software is too new for this hardware. Please downgrade to a UHD/NI-USRP that supports hardware revision %d.")
+                "Software is too new for this hardware. Please downgrade to a driver that supports hardware revision %d.")
                 % mb.hw_rev));
-        }
-    } else if (mb.hw_rev >= 7) {    //Revision compat was added with revision 7
-        if (not recover_mb_eeprom)
-            throw uhd::runtime_error("No revision compat detected MB EEPROM must be reprogrammed!");
     }
 
     ////////////////////////////////////////////////////////////////////
@@ -1772,39 +1779,39 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_pcie(const std::string& res
         if (nirio_status_not_fatal(status)) {
             //The PCIe ID -> MB mapping may be different from the EEPROM -> MB mapping
             switch (pid) {
-                case X300_USRP_PCIE_SSID:
-                case X300_USRP_PCIE_R7_SSID:
+                case X300_USRP_PCIE_SSID_ADC_33:
+                case X300_USRP_PCIE_SSID_ADC_18:
                     mb_type = USRP_X300_MB; break;
-                case X310_USRP_PCIE_SSID:
-                case X310_2940R_40MHz_PCIE_SSID:
-                case X310_2940R_120MHz_PCIE_SSID:
-                case X310_2942R_40MHz_PCIE_SSID:
-                case X310_2942R_120MHz_PCIE_SSID:
-                case X310_2943R_40MHz_PCIE_SSID:
-                case X310_2943R_120MHz_PCIE_SSID:
-                case X310_2944R_40MHz_PCIE_SSID:
-                case X310_2950R_40MHz_PCIE_SSID:
-                case X310_2950R_120MHz_PCIE_SSID:
-                case X310_2952R_40MHz_PCIE_SSID:
-                case X310_2952R_120MHz_PCIE_SSID:
-                case X310_2953R_40MHz_PCIE_SSID:
-                case X310_2953R_120MHz_PCIE_SSID:
-                case X310_2954R_40MHz_PCIE_SSID:
-                case X310_USRP_PCIE_R7_SSID:
-                case X310_2940R_40MHz_PCIE_R7_SSID:
-                case X310_2940R_120MHz_PCIE_R7_SSID:
-                case X310_2942R_40MHz_PCIE_R7_SSID:
-                case X310_2942R_120MHz_PCIE_R7_SSID:
-                case X310_2943R_40MHz_PCIE_R7_SSID:
-                case X310_2943R_120MHz_PCIE_R7_SSID:
-                case X310_2944R_40MHz_PCIE_R7_SSID:
-                case X310_2950R_40MHz_PCIE_R7_SSID:
-                case X310_2950R_120MHz_PCIE_R7_SSID:
-                case X310_2952R_40MHz_PCIE_R7_SSID:
-                case X310_2952R_120MHz_PCIE_R7_SSID:
-                case X310_2953R_40MHz_PCIE_R7_SSID:
-                case X310_2953R_120MHz_PCIE_R7_SSID:
-                case X310_2954R_40MHz_PCIE_R7_SSID:
+                case X310_USRP_PCIE_SSID_ADC_33:
+                case X310_2940R_40MHz_PCIE_SSID_ADC_33:
+                case X310_2940R_120MHz_PCIE_SSID_ADC_33:
+                case X310_2942R_40MHz_PCIE_SSID_ADC_33:
+                case X310_2942R_120MHz_PCIE_SSID_ADC_33:
+                case X310_2943R_40MHz_PCIE_SSID_ADC_33:
+                case X310_2943R_120MHz_PCIE_SSID_ADC_33:
+                case X310_2944R_40MHz_PCIE_SSID_ADC_33:
+                case X310_2950R_40MHz_PCIE_SSID_ADC_33:
+                case X310_2950R_120MHz_PCIE_SSID_ADC_33:
+                case X310_2952R_40MHz_PCIE_SSID_ADC_33:
+                case X310_2952R_120MHz_PCIE_SSID_ADC_33:
+                case X310_2953R_40MHz_PCIE_SSID_ADC_33:
+                case X310_2953R_120MHz_PCIE_SSID_ADC_33:
+                case X310_2954R_40MHz_PCIE_SSID_ADC_33:
+                case X310_USRP_PCIE_SSID_ADC_18:
+                case X310_2940R_40MHz_PCIE_SSID_ADC_18:
+                case X310_2940R_120MHz_PCIE_SSID_ADC_18:
+                case X310_2942R_40MHz_PCIE_SSID_ADC_18:
+                case X310_2942R_120MHz_PCIE_SSID_ADC_18:
+                case X310_2943R_40MHz_PCIE_SSID_ADC_18:
+                case X310_2943R_120MHz_PCIE_SSID_ADC_18:
+                case X310_2944R_40MHz_PCIE_SSID_ADC_18:
+                case X310_2950R_40MHz_PCIE_SSID_ADC_18:
+                case X310_2950R_120MHz_PCIE_SSID_ADC_18:
+                case X310_2952R_40MHz_PCIE_SSID_ADC_18:
+                case X310_2952R_120MHz_PCIE_SSID_ADC_18:
+                case X310_2953R_40MHz_PCIE_SSID_ADC_18:
+                case X310_2953R_120MHz_PCIE_SSID_ADC_18:
+                case X310_2954R_40MHz_PCIE_SSID_ADC_18:
                     mb_type = USRP_X310_MB; break;
                 default:
                     mb_type = UNKNOWN;      break;
@@ -1829,39 +1836,39 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_eeprom(const uhd::usrp::mbo
 
         switch (product_num) {
             //The PCIe ID -> MB mapping may be different from the EEPROM -> MB mapping
-            case X300_USRP_PCIE_SSID:
-            case X300_USRP_PCIE_R7_SSID:
+            case X300_USRP_PCIE_SSID_ADC_33:
+            case X300_USRP_PCIE_SSID_ADC_18:
                 mb_type = USRP_X300_MB; break;
-            case X310_USRP_PCIE_SSID:
-            case X310_2940R_40MHz_PCIE_SSID:
-            case X310_2940R_120MHz_PCIE_SSID:
-            case X310_2942R_40MHz_PCIE_SSID:
-            case X310_2942R_120MHz_PCIE_SSID:
-            case X310_2943R_40MHz_PCIE_SSID:
-            case X310_2943R_120MHz_PCIE_SSID:
-            case X310_2944R_40MHz_PCIE_SSID:
-            case X310_2950R_40MHz_PCIE_SSID:
-            case X310_2950R_120MHz_PCIE_SSID:
-            case X310_2952R_40MHz_PCIE_SSID:
-            case X310_2952R_120MHz_PCIE_SSID:
-            case X310_2953R_40MHz_PCIE_SSID:
-            case X310_2953R_120MHz_PCIE_SSID:
-            case X310_2954R_40MHz_PCIE_SSID:
-            case X310_USRP_PCIE_R7_SSID:
-            case X310_2940R_40MHz_PCIE_R7_SSID:
-            case X310_2940R_120MHz_PCIE_R7_SSID:
-            case X310_2942R_40MHz_PCIE_R7_SSID:
-            case X310_2942R_120MHz_PCIE_R7_SSID:
-            case X310_2943R_40MHz_PCIE_R7_SSID:
-            case X310_2943R_120MHz_PCIE_R7_SSID:
-            case X310_2944R_40MHz_PCIE_R7_SSID:
-            case X310_2950R_40MHz_PCIE_R7_SSID:
-            case X310_2950R_120MHz_PCIE_R7_SSID:
-            case X310_2952R_40MHz_PCIE_R7_SSID:
-            case X310_2952R_120MHz_PCIE_R7_SSID:
-            case X310_2953R_40MHz_PCIE_R7_SSID:
-            case X310_2953R_120MHz_PCIE_R7_SSID:
-            case X310_2954R_40MHz_PCIE_R7_SSID:
+            case X310_USRP_PCIE_SSID_ADC_33:
+            case X310_2940R_40MHz_PCIE_SSID_ADC_33:
+            case X310_2940R_120MHz_PCIE_SSID_ADC_33:
+            case X310_2942R_40MHz_PCIE_SSID_ADC_33:
+            case X310_2942R_120MHz_PCIE_SSID_ADC_33:
+            case X310_2943R_40MHz_PCIE_SSID_ADC_33:
+            case X310_2943R_120MHz_PCIE_SSID_ADC_33:
+            case X310_2944R_40MHz_PCIE_SSID_ADC_33:
+            case X310_2950R_40MHz_PCIE_SSID_ADC_33:
+            case X310_2950R_120MHz_PCIE_SSID_ADC_33:
+            case X310_2952R_40MHz_PCIE_SSID_ADC_33:
+            case X310_2952R_120MHz_PCIE_SSID_ADC_33:
+            case X310_2953R_40MHz_PCIE_SSID_ADC_33:
+            case X310_2953R_120MHz_PCIE_SSID_ADC_33:
+            case X310_2954R_40MHz_PCIE_SSID_ADC_33:
+            case X310_USRP_PCIE_SSID_ADC_18:
+            case X310_2940R_40MHz_PCIE_SSID_ADC_18:
+            case X310_2940R_120MHz_PCIE_SSID_ADC_18:
+            case X310_2942R_40MHz_PCIE_SSID_ADC_18:
+            case X310_2942R_120MHz_PCIE_SSID_ADC_18:
+            case X310_2943R_40MHz_PCIE_SSID_ADC_18:
+            case X310_2943R_120MHz_PCIE_SSID_ADC_18:
+            case X310_2944R_40MHz_PCIE_SSID_ADC_18:
+            case X310_2950R_40MHz_PCIE_SSID_ADC_18:
+            case X310_2950R_120MHz_PCIE_SSID_ADC_18:
+            case X310_2952R_40MHz_PCIE_SSID_ADC_18:
+            case X310_2952R_120MHz_PCIE_SSID_ADC_18:
+            case X310_2953R_40MHz_PCIE_SSID_ADC_18:
+            case X310_2953R_120MHz_PCIE_SSID_ADC_18:
+            case X310_2954R_40MHz_PCIE_SSID_ADC_18:
                 mb_type = USRP_X310_MB; break;
             default:
                 UHD_MSG(warning) << "X300 unknown product code in EEPROM: " << product_num << std::endl;
@@ -2163,7 +2170,7 @@ void x300_impl::self_test_adcs(mboard_members_t& mb, boost::uint32_t ramp_time_m
         else
             q_status = "Not Locked!";
 
-        passed &= (i_status == "Good") && (q_status == "Good");
+        passed = passed && (i_status == "Good") && (q_status == "Good");
         status_str += (boost::format(", ADC%d_I=%s, ADC%d_Q=%s")%r%i_status%r%q_status).str();
 
         //Return to normal mode
@@ -2194,7 +2201,7 @@ void x300_impl::extended_adc_test(mboard_members_t& mb, double duration_s)
         UHD_MSG(status) << boost::format("-- [%s] Iteration %06d... ") % time_strm.str() % (iter+1);
         try {
             self_test_adcs(mb, SECS_PER_ITER*1000);
-            UHD_MSG(status) << "done" << std::endl;
+            UHD_MSG(status) << "passed" << std::endl;
         } catch(std::exception &e) {
             num_failures++;
             UHD_MSG(status) << e.what() << std::endl;
@@ -2205,6 +2212,6 @@ void x300_impl::extended_adc_test(mboard_members_t& mb, double duration_s)
         UHD_MSG(status) << "Extended ADC Self-Test PASSED\n";
     } else {
         throw uhd::runtime_error(
-                (boost::format("Extended ADC FAILED!!! (%d/%d failures)\n") % num_failures % num_iters).str());
+                (boost::format("Extended ADC Self-Test FAILED!!! (%d/%d failures)\n") % num_failures % num_iters).str());
     }
 }
diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp
index d5dc8140c..f41afeb23 100644
--- a/host/lib/usrp/x300/x300_regs.hpp
+++ b/host/lib/usrp/x300/x300_regs.hpp
@@ -106,40 +106,40 @@ localparam ZPU_RB_ETH_TYPE1  = 5;
 
 static const uint32_t X300_PCIE_VID               = 0x1093;
 static const uint32_t X300_PCIE_PID               = 0xC4C4;
-//Rev 0-6 motherboard/PCIe IDs
-static const uint32_t X300_USRP_PCIE_SSID         = 0x7736;
-static const uint32_t X310_USRP_PCIE_SSID         = 0x76CA;
-static const uint32_t X310_2940R_40MHz_PCIE_SSID  = 0x772B;
-static const uint32_t X310_2940R_120MHz_PCIE_SSID = 0x77FB;
-static const uint32_t X310_2942R_40MHz_PCIE_SSID  = 0x772C;
-static const uint32_t X310_2942R_120MHz_PCIE_SSID = 0x77FC;
-static const uint32_t X310_2943R_40MHz_PCIE_SSID  = 0x772D;
-static const uint32_t X310_2943R_120MHz_PCIE_SSID = 0x77FD;
-static const uint32_t X310_2944R_40MHz_PCIE_SSID  = 0x772E;
-static const uint32_t X310_2950R_40MHz_PCIE_SSID  = 0x772F;
-static const uint32_t X310_2950R_120MHz_PCIE_SSID = 0x77FE;
-static const uint32_t X310_2952R_40MHz_PCIE_SSID  = 0x7730;
-static const uint32_t X310_2952R_120MHz_PCIE_SSID = 0x77FF;
-static const uint32_t X310_2953R_40MHz_PCIE_SSID  = 0x7731;
-static const uint32_t X310_2953R_120MHz_PCIE_SSID = 0x7800;
-static const uint32_t X310_2954R_40MHz_PCIE_SSID  = 0x7732;
-//Rev 7+ motherboard/PCIe IDs
-static const uint32_t X300_USRP_PCIE_R7_SSID         = 0x7861;
-static const uint32_t X310_USRP_PCIE_R7_SSID         = 0x7862;
-static const uint32_t X310_2940R_40MHz_PCIE_R7_SSID  = 0x7853;
-static const uint32_t X310_2940R_120MHz_PCIE_R7_SSID = 0x785B;
-static const uint32_t X310_2942R_40MHz_PCIE_R7_SSID  = 0x7854;
-static const uint32_t X310_2942R_120MHz_PCIE_R7_SSID = 0x785C;
-static const uint32_t X310_2943R_40MHz_PCIE_R7_SSID  = 0x7855;
-static const uint32_t X310_2943R_120MHz_PCIE_R7_SSID = 0x785D;
-static const uint32_t X310_2944R_40MHz_PCIE_R7_SSID  = 0x7856;
-static const uint32_t X310_2950R_40MHz_PCIE_R7_SSID  = 0x7857;
-static const uint32_t X310_2950R_120MHz_PCIE_R7_SSID = 0x785E;
-static const uint32_t X310_2952R_40MHz_PCIE_R7_SSID  = 0x7858;
-static const uint32_t X310_2952R_120MHz_PCIE_R7_SSID = 0x785F;
-static const uint32_t X310_2953R_40MHz_PCIE_R7_SSID  = 0x7859;
-static const uint32_t X310_2953R_120MHz_PCIE_R7_SSID = 0x7860;
-static const uint32_t X310_2954R_40MHz_PCIE_R7_SSID  = 0x785A;
+//Rev 0-6 motherboard/PCIe IDs (ADC driven at 3.3V)
+static const uint32_t X300_USRP_PCIE_SSID_ADC_33         = 0x7736;
+static const uint32_t X310_USRP_PCIE_SSID_ADC_33         = 0x76CA;
+static const uint32_t X310_2940R_40MHz_PCIE_SSID_ADC_33  = 0x772B;
+static const uint32_t X310_2940R_120MHz_PCIE_SSID_ADC_33 = 0x77FB;
+static const uint32_t X310_2942R_40MHz_PCIE_SSID_ADC_33  = 0x772C;
+static const uint32_t X310_2942R_120MHz_PCIE_SSID_ADC_33 = 0x77FC;
+static const uint32_t X310_2943R_40MHz_PCIE_SSID_ADC_33  = 0x772D;
+static const uint32_t X310_2943R_120MHz_PCIE_SSID_ADC_33 = 0x77FD;
+static const uint32_t X310_2944R_40MHz_PCIE_SSID_ADC_33  = 0x772E;
+static const uint32_t X310_2950R_40MHz_PCIE_SSID_ADC_33  = 0x772F;
+static const uint32_t X310_2950R_120MHz_PCIE_SSID_ADC_33 = 0x77FE;
+static const uint32_t X310_2952R_40MHz_PCIE_SSID_ADC_33  = 0x7730;
+static const uint32_t X310_2952R_120MHz_PCIE_SSID_ADC_33 = 0x77FF;
+static const uint32_t X310_2953R_40MHz_PCIE_SSID_ADC_33  = 0x7731;
+static const uint32_t X310_2953R_120MHz_PCIE_SSID_ADC_33 = 0x7800;
+static const uint32_t X310_2954R_40MHz_PCIE_SSID_ADC_33  = 0x7732;
+//Rev 7+ motherboard/PCIe IDs (ADCs driven at 1.8V)
+static const uint32_t X300_USRP_PCIE_SSID_ADC_18         = 0x7861;
+static const uint32_t X310_USRP_PCIE_SSID_ADC_18         = 0x7862;
+static const uint32_t X310_2940R_40MHz_PCIE_SSID_ADC_18  = 0x7853;
+static const uint32_t X310_2940R_120MHz_PCIE_SSID_ADC_18 = 0x785B;
+static const uint32_t X310_2942R_40MHz_PCIE_SSID_ADC_18  = 0x7854;
+static const uint32_t X310_2942R_120MHz_PCIE_SSID_ADC_18 = 0x785C;
+static const uint32_t X310_2943R_40MHz_PCIE_SSID_ADC_18  = 0x7855;
+static const uint32_t X310_2943R_120MHz_PCIE_SSID_ADC_18 = 0x785D;
+static const uint32_t X310_2944R_40MHz_PCIE_SSID_ADC_18  = 0x7856;
+static const uint32_t X310_2950R_40MHz_PCIE_SSID_ADC_18  = 0x7857;
+static const uint32_t X310_2950R_120MHz_PCIE_SSID_ADC_18 = 0x785E;
+static const uint32_t X310_2952R_40MHz_PCIE_SSID_ADC_18  = 0x7858;
+static const uint32_t X310_2952R_120MHz_PCIE_SSID_ADC_18 = 0x785F;
+static const uint32_t X310_2953R_40MHz_PCIE_SSID_ADC_18  = 0x7859;
+static const uint32_t X310_2953R_120MHz_PCIE_SSID_ADC_18 = 0x7860;
+static const uint32_t X310_2954R_40MHz_PCIE_SSID_ADC_18  = 0x785A;
 
 static const uint32_t FPGA_X3xx_SIG_VALUE   = 0x58333030;