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authorJosh Blum <josh@joshknows.com>2011-01-19 19:55:15 -0800
committerJosh Blum <josh@joshknows.com>2011-01-19 19:55:15 -0800
commitfbb96ac77fd46c2beb43634e2ae8a0cae1709d39 (patch)
tree1e10ab3d42cdf84cf975b578caff6ee995eb18d8
parent373ddac69e8f94b8fc7731f67259ef8934caa6f2 (diff)
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uhd: removed deleted fpga files removed from fpga repo
-rw-r--r--fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs15
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf0
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf0
3 files changed, 0 insertions, 15 deletions
diff --git a/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs
deleted file mode 100644
index d946af064..000000000
--- a/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs
+++ /dev/null
@@ -1,15 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated -->
-<!-- by the Xilinx ISE software. Any direct editing or -->
-<!-- changes made to this file may result in unpredictable -->
-<!-- behavior or data corruption. It is strongly advised that -->
-<!-- users do not edit the contents of this file. -->
-<!-- -->
-<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
-
-<messages>
-<msg type="info" file="ProjectMgmt" num="1062" ><arg fmt="%s" index="1">Parsing Verilog file &quot;/home/jblum/uhdpriv/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v&quot; into library work</arg>
-</msg>
-
-</messages>
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf
deleted file mode 100644
index e69de29bb..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf
+++ /dev/null
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf
deleted file mode 100644
index e69de29bb..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf
+++ /dev/null