u2/u2p: allow cpu to receive or send packets longer than the buffer size.

on reception, the rest is dropped.  On sending, the rest is a repeat of the buffer.

1 files changed, 10 insertions, 7 deletions

diff --git a/usrp2/fifo/buffer_int2.v b/usrp2/fifo/buffer_int2.v
index c73456b74..532980aa2 100644
--- a/usrp2/fifo/buffer_int2.v
+++ b/usrp2/fifo/buffer_int2.v
@@ -31,14 +31,15 @@ module buffer_int2
      input rd_ready_i
      );
 
-   reg [BUF_SIZE-1:0] rd_addr, wr_addr;
-   wire [BUF_SIZE-1:0] rd_addr_next = rd_addr + 1;
+   reg [15:0]         rd_addr, wr_addr;    // Handle pkt bigger than buffer
+   wire [15:0] 	      rd_addr_next = rd_addr + 1;
+   reg [15:0] 	      rd_length;
+
    wire [31:0] 	      ctrl;
    wire 	      wr_done, wr_error, wr_idle;
    wire 	      rd_done, rd_error, rd_idle;
    wire 	      we, en, go;
 
-   reg [BUF_SIZE-1:0] rd_length;
    wire 	      read = ctrl[3];
    wire 	      rd_clear = ctrl[2];
    wire 	      write = ctrl[1];
@@ -73,7 +74,7 @@ module buffer_int2
 	     begin
 		rd_addr <= 0;
 		rd_state <= PRE_READ;
-		rd_length <= ctrl[15+BUF_SIZE:16];
+		rd_length <= ctrl[31:16];
 	     end
 	 
 	 PRE_READ :
@@ -146,17 +147,19 @@ module buffer_int2
    assign     rd_idle = (rd_state == IDLE);
    assign     wr_idle = (wr_state == IDLE);
 
+   wire [BUF_SIZE-1:0] wr_addr_clip = (|wr_addr[15:BUF_SIZE]) ? {BUF_SIZE{1'b1}} : wr_addr[BUF_SIZE-1:0];
+   
    ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer_in // CPU reads here
      (.clka(wb_clk_i),.ena(wb_stb_i),.wea(1'b0),
       .addra(wb_adr_i[BUF_SIZE+1:2]),.dia(0),.doa(wb_dat_o),
       .clkb(clk),.enb(1'b1),.web(we),
-      .addrb(wr_addr),.dib(wr_data_i[31:0]),.dob());
+      .addrb(wr_addr_clip),.dib(wr_data_i[31:0]),.dob());
    
    ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer_out // CPU writes here
      (.clka(wb_clk_i),.ena(wb_stb_i),.wea(wb_we_i),
       .addra(wb_adr_i[BUF_SIZE+1:2]),.dia(wb_dat_i),.doa(),
       .clkb(clk),.enb(en),.web(1'b0),
-      .addrb(rd_addr),.dib(0),.dob(rd_data_o[31:0]));
+      .addrb(rd_addr[BUF_SIZE-1:0]),.dib(0),.dob(rd_data_o[31:0]));
    
    always @(posedge wb_clk_i)
      if(wb_rst_i)
@@ -168,7 +171,7 @@ module buffer_int2
    sreg(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
 	.out(ctrl),.changed(go));
    
-   assign status = { {(16-BUF_SIZE){1'b0}},wr_addr,
+   assign status = { wr_addr,
 		     8'b0,1'b0,rd_idle,rd_error,rd_done, 1'b0,wr_idle,wr_error,wr_done};
 
 endmodule // buffer_int2