added ability to clear out fifos of tx and rx.

3 files changed, 37 insertions, 28 deletions

diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index 9f7b6dc4c..23bad56ae 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -16,7 +16,7 @@ module gpmc_async
     output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
     
     // FIFO interface
-    input fifo_clk, input fifo_rst,
+    input fifo_clk, input fifo_rst, input clear_tx, input clear_rx,
     output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
     input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
     
@@ -34,7 +34,7 @@ module gpmc_async
    wire 	  bus_error_tx, bus_error_rx;
    
    always @(posedge fifo_clk)
-     if(fifo_rst)
+     if(fifo_rst | clear_tx | clear_rx)
        bus_error <= 0;
      else
        bus_error <= bus_error_tx | bus_error_rx;
@@ -54,23 +54,23 @@ module gpmc_async
    
    gpmc_to_fifo_async gpmc_to_fifo_async
      (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
-      .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+      .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx),
       .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
       .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space),
       .bus_error(bus_error_tx) );
    
    fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
       .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
       .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied());
 
    fifo19_to_fifo36 #(.LE(1)) f19_to_f36   // Little endian because ARM is LE
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
       .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
       .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
    
    fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
       .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
       .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
 
@@ -85,22 +85,22 @@ module gpmc_async
    wire 	  dummy;
    
    fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
       .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
       .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
 
    fifo36_to_fifo19 #(.LE(1)) f36_to_f19   // Little endian because ARM is LE
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
       .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
       .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
 
    fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
       .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space),
       .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied());
 
    fifo_to_gpmc_async fifo_to_gpmc_async
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
       .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy),
       .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
       .frame_len(rx_frame_len) );
@@ -108,7 +108,7 @@ module gpmc_async
    wire [31:0] 	pkt_count;
    
    fifo_watcher fifo_watcher
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
       .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]),
       .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]),
       .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx),
diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v
index 3d29745a2..55c0cef50 100644
--- a/usrp2/gpmc/gpmc_to_fifo_async.v
+++ b/usrp2/gpmc/gpmc_to_fifo_async.v
@@ -2,7 +2,7 @@
 module gpmc_to_fifo_async
   (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE,
 
-   input fifo_clk, input fifo_rst,
+   input fifo_clk, input fifo_rst, input clear,
    output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i,
 
    input [15:0] frame_len, input [15:0] fifo_space, output reg fifo_ready,
@@ -37,7 +37,7 @@ module gpmc_to_fifo_async
        end
 
    always @(posedge fifo_clk)
-     if(fifo_rst)
+     if(fifo_rst | clear)
        src_rdy_o <= 0;
      else if(do_write)
        src_rdy_o <= 1;
@@ -45,7 +45,7 @@ module gpmc_to_fifo_async
        src_rdy_o <= 0;    // Assume it was taken
 
    always @(posedge fifo_clk)
-     if(fifo_rst)
+     if(fifo_rst | clear)
        counter <= 0;
      else if(do_write)
        if(last_write)
@@ -54,13 +54,13 @@ module gpmc_to_fifo_async
 	 counter <= counter + 1;
 
    always @(posedge fifo_clk)
-     if(fifo_rst)
+     if(fifo_rst | clear)
        fifo_ready <= 0;
      else
        fifo_ready <= /* first_write & */ (fifo_space > 16'd1023);
 
    always @(posedge fifo_clk)
-     if(fifo_rst)
+     if(fifo_rst | clear)
        bus_error <= 0;
      else if(src_rdy_o & ~dst_rdy_i)
        bus_error <= 1;
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 64173ef2d..787bf016c 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -28,10 +28,11 @@ module u1e_core
    localparam TXFIFOSIZE = 13;
    localparam RXFIFOSIZE = 13;
 
-   localparam SR_RX_DSP = 0;    // 5 regs
-   localparam SR_RX_CTRL = 8;   // 9 regs
-   localparam SR_TX_DSP = 17;   // 5 regs
-   localparam SR_TX_CTRL = 24;  // 2 regs
+   localparam SR_RX_DSP = 0;     // 5 regs
+   localparam SR_CLEAR_FIFO = 6; // 1 reg
+   localparam SR_RX_CTRL = 8;    // 9 regs
+   localparam SR_TX_DSP = 17;    // 5 regs
+   localparam SR_TX_CTRL = 24;   // 2 regs
    localparam SR_TIME64 = 28;    // 4 regs
       
    wire 	wb_clk = clk_fpga;
@@ -65,6 +66,14 @@ module u1e_core
    wire [7:0] 	 rate;
 
    wire 	 bus_error;
+
+   wire 	 clear_rx_int, clear_tx_int, clear_tx, clear_rx, do_clear;
+   
+   setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(2)) sr_clear
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({clear_tx_int,clear_rx_int}),.changed(do_clear));
+   assign clear_tx = clear_tx_int & do_clear;
+   assign clear_rx = clear_rx_int & do_clear;
    
    gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
    gpmc (.arst(wb_rst),
@@ -80,7 +89,7 @@ module u1e_core
 	 .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
 	 .wb_ack_i(m0_ack),
 	 
-	 .fifo_clk(wb_clk), .fifo_rst(wb_rst),
+	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx),
 	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
 	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
 	 
@@ -93,7 +102,7 @@ module u1e_core
    
 `ifdef LOOPBACK
    fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx),
       .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
       .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
 
@@ -113,7 +122,7 @@ module u1e_core
       .underrun(tx_underrun), .overrun());
    
    packet_verifier32 pktver32
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear),
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
       .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int),
       .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
 
@@ -121,7 +130,7 @@ module u1e_core
    wire 	 rx_enable;
 
    packet_generator32 pktgen32
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear),
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
       .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int));
 
    fifo_pacer rx_pacer
@@ -152,7 +161,7 @@ module u1e_core
       .debug(debug_rx_dsp) );
 
    vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .vita_time(vita_time), .overrun(rx_overrun),
       .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
@@ -160,7 +169,7 @@ module u1e_core
       .debug_rx(vrc_debug));
 
    vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy),
       .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy),
@@ -177,14 +186,14 @@ module u1e_core
    wire 	 run_tx;
    
    vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
       .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
       .debug(debug_vtd) );
 
    vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .vita_time(vita_time),.underrun(tx_underrun),
       .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),