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| author | Martin Braun <martin.braun@ettus.com> | 2014-06-06 19:40:03 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-06-06 19:40:03 +0200 |
| commit | 3e12a0a7a55334afaa219e21d8550ebe40e4e24f (patch) | |
| tree | 745fae6fe1d7c7b59e2f19293ff2cad82a88d28e | |
| parent | 8faf5bc4999c14681c3edbcd585175f749c1969d (diff) | |
| download | uhd-3e12a0a7a55334afaa219e21d8550ebe40e4e24f.tar.gz uhd-3e12a0a7a55334afaa219e21d8550ebe40e4e24f.tar.bz2 uhd-3e12a0a7a55334afaa219e21d8550ebe40e4e24f.zip | |
b200/docs: Fixed ISE version in docs to 14.4
| -rw-r--r-- | host/docs/images.dox | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/host/docs/images.dox b/host/docs/images.dox index 02454c674..321452b87 100644 --- a/host/docs/images.dox +++ b/host/docs/images.dox @@ -80,11 +80,11 @@ depending on the device. The build requires that you have a UNIX-like environment with `Make`. Make sure that `xtclsh` from the Xilinx ISE bin directory is in your `$PATH`. -- Xilinx ISE 14.4: USRP X3x0 Series +- Xilinx ISE 14.4: USRP X3x0 Series, USRP B2x0 See `<uhd-repo-path>/fpga/usrp3/top/`. -- Xilinx ISSE 12.2: USRP N2x0, USRP B2x0, USRP B1x0, USRP E1x0, USRP2 +- Xilinx ISSE 12.2: USRP N2x0, USRP B1x0, USRP E1x0, USRP2 See `<uhd-repo-path>/fpga/usrp2/top/`. |