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| author | Josh Blum <josh@joshknows.com> | 2010-08-09 18:18:04 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-08-09 18:18:04 -0700 |
| commit | 0f0e3abe76c88bee67e278952c1db4ae59c624be (patch) | |
| tree | 6193696c6db568e54e153a570021251e0b6cfe44 | |
| parent | 52a1e1c10b3298ad689e88fd9d8ccdd94d08f56b (diff) | |
| download | uhd-0f0e3abe76c88bee67e278952c1db4ae59c624be.tar.gz uhd-0f0e3abe76c88bee67e278952c1db4ae59c624be.tar.bz2 uhd-0f0e3abe76c88bee67e278952c1db4ae59c624be.zip | |
added compat number to usrp2 readback mux
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core_udp.v | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index b79cab5fb..124930c23 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -423,7 +423,10 @@ module u2_core cycle_count <= 0; else cycle_count <= cycle_count + 1; - + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd1; + wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), @@ -431,7 +434,7 @@ module u2_core .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) ); // ///////////////////////////////////////////////////////////////////////// |