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| author | Josh Blum <josh@joshknows.com> | 2013-04-02 18:11:19 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2013-04-02 18:11:19 -0700 |
| commit | df2c9b3af895a826db09ad5817f84a3aa7b6b3d9 (patch) | |
| tree | 9b0209b25f819c792bea5454668a7653be1b0ef8 | |
| parent | 81447a405eab9cfe154ebcf1d809d95269ed349a (diff) | |
| download | uhd-df2c9b3af895a826db09ad5817f84a3aa7b6b3d9.tar.gz uhd-df2c9b3af895a826db09ad5817f84a3aa7b6b3d9.tar.bz2 uhd-df2c9b3af895a826db09ad5817f84a3aa7b6b3d9.zip | |
E110: revert Makefile for E110, the UCF was accidentally removed
| -rw-r--r-- | usrp2/top/E1x0/Makefile.E110 | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110 index c2d3e39e6..e5be8d2fa 100644 --- a/usrp2/top/E1x0/Makefile.E110 +++ b/usrp2/top/E1x0/Makefile.E110 @@ -50,6 +50,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \ TOP_SRCS = \ ../B100/u1plus_core.v \ E1x0.v \ +E1x0.ucf \ timing.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ |