Merge branch 'ise12' into next

3 files changed, 23 insertions, 29 deletions

diff --git a/fpga/usrp2/sdr_lib/dsp_core_rx.v b/fpga/usrp2/sdr_lib/dsp_core_rx.v
index 1e689fc7f..1318809d6 100644
--- a/fpga/usrp2/sdr_lib/dsp_core_rx.v
+++ b/fpga/usrp2/sdr_lib/dsp_core_rx.v
@@ -57,41 +57,32 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .adc_in(adc_b),.adc_out(adc_b_ofs));
 
-   wire [3:0]  muxctrl;
-   setting_reg #(.my_addr(BASE+5)) sr_8
+   wire [7:0]  muxctrl;
+   setting_reg #(.my_addr(BASE+5), .width(8)) sr_8
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({UNUSED_2,muxctrl}),.changed());
 
    wire [1:0] gpio_ena;
-   setting_reg #(.my_addr(BASE+6)) sr_9
+   setting_reg #(.my_addr(BASE+6), .width(2)) sr_9
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({UNUSED_3,gpio_ena}),.changed());
 
-   // The TVRX connects to what is called adc_b, thus A and B are
-   // swapped throughout the design.
-   //
-   // In the interest of expediency and keeping the s/w sane, we just remap them here.
-   // The I & Q fields are mapped the same:
-   // 0 -> "the real A" (as determined by the TVRX)
-   // 1 -> "the real B"
-   // 2 -> const zero
-   
    always @(posedge clk)
-     case(muxctrl[1:0])		// The I mapping
-       0: adc_i <= adc_b_ofs;	// "the real A"
-       1: adc_i <= adc_a_ofs;
+     case(muxctrl[3:0])		// The I mapping
+       0: adc_i <= adc_a_ofs;
+       1: adc_i <= adc_b_ofs;
        2: adc_i <= 0;
        default: adc_i <= 0;
-     endcase // case(muxctrl[1:0])
-          
+     endcase // case (muxctrl[3:0])
+   
    always @(posedge clk)
-     case(muxctrl[3:2])		// The Q mapping
-       0: adc_q <= adc_b_ofs;	// "the real A"
-       1: adc_q <= adc_a_ofs;
+     case(muxctrl[7:4])		// The Q mapping
+       0: adc_q <= adc_a_ofs;
+       1: adc_q <= adc_b_ofs;
        2: adc_q <= 0;
        default: adc_q <= 0;
-     endcase // case(muxctrl[3:2])
-       
+     endcase // case (muxctrl[7:4])
+          
    always @(posedge clk)
      if(rst)
        phase <= 0;
diff --git a/fpga/usrp2/top/u2_rev3/u2_core_udp.v b/fpga/usrp2/top/u2_rev3/u2_core_udp.v
index 124930c23..c9502898b 100644
--- a/fpga/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core_udp.v
@@ -425,7 +425,7 @@ module u2_core
        cycle_count <= cycle_count + 1;
 
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = 32'd1;
+   localparam compat_num = 32'd2;
 
    wb_readback_mux buff_pool_status
      (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.v b/fpga/usrp2/top/u2_rev3/u2_rev3.v
index 3a43e4ffe..4daa66212 100644
--- a/fpga/usrp2/top/u2_rev3/u2_rev3.v
+++ b/fpga/usrp2/top/u2_rev3/u2_rev3.v
@@ -203,12 +203,13 @@ module u2_rev3
    reg [13:0] 	 adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
    reg 		 adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
 
+    // ADC A and B are swapped in schematic to facilitate clean layout
    always @(posedge dsp_clk)
      begin
-	adc_a_reg1 <= adc_a;
-	adc_b_reg1 <= adc_b;
-	adc_ovf_a_reg1 <= adc_ovf_a;
-	adc_ovf_b_reg1 <= adc_ovf_b;
+	adc_a_reg1 <= adc_b;
+	adc_b_reg1 <= adc_a;
+	adc_ovf_a_reg1 <= adc_ovf_b;
+	adc_ovf_b_reg1 <= adc_ovf_a;
      end
    
    always @(posedge dsp_clk)
@@ -327,8 +328,10 @@ module u2_rev3
      end
 
    wire [15:0] dac_a_int, dac_b_int;
-   always @(negedge dsp_clk) dac_a <= dac_a_int;
-   always @(negedge dsp_clk) dac_b <= dac_b_int;
+   // DAC A and B are swapped in schematic to facilitate clean layout
+   // DAC A is also inverted in schematic to facilitate clean layout
+   always @(negedge dsp_clk) dac_a <= ~dac_b_int;
+   always @(negedge dsp_clk) dac_b <= dac_a_int;
 
    /*
    OFDDRRSE OFDDRRSE_serdes_inst