Merge branch 'udp' of git@ettus.sourcerepo.com:ettus/fpgapriv

6 files changed, 47 insertions, 32 deletions

diff --git a/fpga/usrp2/control_lib/nsgpio.v b/fpga/usrp2/control_lib/nsgpio.v
index 937ea7020..26130cc8e 100644
--- a/fpga/usrp2/control_lib/nsgpio.v
+++ b/fpga/usrp2/control_lib/nsgpio.v
@@ -95,7 +95,7 @@ module nsgpio
    integer   n;
    reg [31:0] igpio; // temporary internal signal
    
-   always @(ctrl or line or debug_1 or debug_0 or atr)
+   always @(ctrl or line or debug_1 or debug_0 or atr or ddr)
      for(n=0;n<32;n=n+1)
        igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : 
 			     (ctrl[2*n] ?  atr[n] : line[n]) )
diff --git a/fpga/usrp2/sdr_lib/cordic_z24.v b/fpga/usrp2/sdr_lib/cordic_z24.v
index cf668d5ec..97b7beaf7 100644
--- a/fpga/usrp2/sdr_lib/cordic_z24.v
+++ b/fpga/usrp2/sdr_lib/cordic_z24.v
@@ -45,30 +45,30 @@ module cordic_z24(clock, reset, enable, xi, yi, zi, xo, yo, zo );
    // see gen_cordic_consts.py
 
    // constants for 24 bit wide phase
-   localparam 	       c00 = 24'd2097152;
-   localparam 	       c01 = 24'd1238021;
-   localparam 	       c02 = 24'd654136;
-   localparam 	       c03 = 24'd332050;
-   localparam 	       c04 = 24'd166669;
-   localparam 	       c05 = 24'd83416;
-   localparam 	       c06 = 24'd41718;
-   localparam 	       c07 = 24'd20860;
-   localparam 	       c08 = 24'd10430;
-   localparam 	       c09 = 24'd5215;
-   localparam 	       c10 = 24'd2608;
-   localparam 	       c11 = 24'd1304;
-   localparam 	       c12 = 24'd652;
-   localparam 	       c13 = 24'd326;
-   localparam 	       c14 = 24'd163;
-   localparam 	       c15 = 24'd81;
-   localparam 	       c16 = 24'd41;
-   localparam 	       c17 = 24'd20;
-   localparam 	       c18 = 24'd10;
-   localparam 	       c19 = 24'd5;
-   localparam 	       c20 = 24'd3;
-   localparam 	       c21 = 24'd1;
-   localparam 	       c22 = 24'd1;
-   localparam 	       c23 = 24'd0;
+   localparam 	       c00 = 23'd2097152;
+   localparam 	       c01 = 23'd1238021;
+   localparam 	       c02 = 23'd654136;
+   localparam 	       c03 = 23'd332050;
+   localparam 	       c04 = 23'd166669;
+   localparam 	       c05 = 23'd83416;
+   localparam 	       c06 = 23'd41718;
+   localparam 	       c07 = 23'd20860;
+   localparam 	       c08 = 23'd10430;
+   localparam 	       c09 = 23'd5215;
+   localparam 	       c10 = 23'd2608;
+   localparam 	       c11 = 23'd1304;
+   localparam 	       c12 = 23'd652;
+   localparam 	       c13 = 23'd326;
+   localparam 	       c14 = 23'd163;
+   localparam 	       c15 = 23'd81;
+   localparam 	       c16 = 23'd41;
+   localparam 	       c17 = 23'd20;
+   localparam 	       c18 = 23'd10;
+   localparam 	       c19 = 23'd5;
+   localparam 	       c20 = 23'd3;
+   localparam 	       c21 = 23'd1;
+   localparam 	       c22 = 23'd1;
+   localparam 	       c23 = 23'd0;
 
    always @(posedge clock)
      if(reset)
diff --git a/fpga/usrp2/sdr_lib/dsp_core_rx.v b/fpga/usrp2/sdr_lib/dsp_core_rx.v
index 2ac429630..1e689fc7f 100644
--- a/fpga/usrp2/sdr_lib/dsp_core_rx.v
+++ b/fpga/usrp2/sdr_lib/dsp_core_rx.v
@@ -32,6 +32,10 @@ module dsp_core_rx
    wire        strobe_cic, strobe_hb1, strobe_hb2;
    wire        enable_hb1, enable_hb2;
    wire [7:0]  cic_decim_rate;
+
+   wire [31:10] UNUSED_1;
+   wire [31:4] 	UNUSED_2;
+   wire [31:2] 	UNUSED_3;
    
    setting_reg #(.my_addr(BASE+0)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -43,7 +47,7 @@ module dsp_core_rx
    
    setting_reg #(.my_addr(BASE+2)) sr_2
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
+      .in(set_data),.out({UNUSED_1, enable_hb1, enable_hb2, cic_decim_rate}),.changed());
 
    rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a
      (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
@@ -56,12 +60,12 @@ module dsp_core_rx
    wire [3:0]  muxctrl;
    setting_reg #(.my_addr(BASE+5)) sr_8
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(muxctrl),.changed());
+      .in(set_data),.out({UNUSED_2,muxctrl}),.changed());
 
    wire [1:0] gpio_ena;
    setting_reg #(.my_addr(BASE+6)) sr_9
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(gpio_ena),.changed());
+      .in(set_data),.out({UNUSED_3,gpio_ena}),.changed());
 
    // The TVRX connects to what is called adc_b, thus A and B are
    // swapped throughout the design.
diff --git a/fpga/usrp2/top/u2_rev3/Makefile b/fpga/usrp2/top/u2_rev3/Makefile
index 1fd8638d9..867fb5cab 100644
--- a/fpga/usrp2/top/u2_rev3/Makefile
+++ b/fpga/usrp2/top/u2_rev3/Makefile
@@ -199,7 +199,7 @@ top/u2_rev3/u2_rev3.v
 # Process Properties
 ##################################################
 export SYNTHESIZE_PROPERTIES := \
-"Number of Clock Buffers" 6 \
+"Number of Clock Buffers" 8 \
 "Pack I/O Registers into IOBs" Yes \
 "Optimization Effort" High \
 "Optimize Instantiated Primitives" TRUE \
diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
index 255a298ac..6aa699d2a 100644
--- a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
+++ b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -331,3 +331,5 @@ NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
 
 #NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
 #NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns;
diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.v b/fpga/usrp2/top/u2_rev3/u2_rev3.v
index 23a825007..3a43e4ffe 100644
--- a/fpga/usrp2/top/u2_rev3/u2_rev3.v
+++ b/fpga/usrp2/top/u2_rev3/u2_rev3.v
@@ -171,8 +171,15 @@ module u2_rev3
        wd <= wd + 1;
    assign 	WDI = wd[15];
    
-   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+   wire 	clk_fpga_unbuf;
+
+   IBUFGDS clk_fpga_pin (.O(clk_fpga_unbuf),.I(clk_fpga_p),.IB(clk_fpga_n));
+   BUFG clk_fpga_BUF (.O(clk_fpga),.I(clk_fpga_unbuf));
+
    defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+   wire 	cpld_clock_buf;
+   BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock));
    
    wire 	exp_pps_in;
    IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
@@ -310,7 +317,9 @@ module u2_rev3
    reg [15:0] ser_r_int;
    reg 	      ser_rklsb_int, ser_rkmsb_int;
 
-   always @(posedge ser_rx_clk)
+   wire       ser_rx_clk_buf;
+   BUFG ser_rx_clk_BUF (.O(ser_rx_clk_buf),.I(ser_rx_clk));
+   always @(posedge ser_rx_clk_buf)
      begin
 	ser_r_int <= ser_r;
 	ser_rklsb_int <= ser_rklsb;
@@ -367,7 +376,7 @@ module u2_rev3
 		     .ser_t		(ser_t_unreg[15:0]),
 		     .ser_tklsb		(ser_tklsb_unreg),
 		     .ser_tkmsb		(ser_tkmsb_unreg),
-		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_rx_clk	(ser_rx_clk_buf),
 		     .ser_r		(ser_r_int[15:0]),
 		     .ser_rklsb		(ser_rklsb_int),
 		     .ser_rkmsb		(ser_rkmsb_int),