e100: renamed top level for E100/E110 to E1x0

Some minor tweaks to gpmc_to_fifo + timing

6 files changed, 16 insertions, 16 deletions

diff --git a/usrp2/gpmc/gpmc_to_fifo.v b/usrp2/gpmc/gpmc_to_fifo.v
index 043ec9b6b..680095620 100644
--- a/usrp2/gpmc/gpmc_to_fifo.v
+++ b/usrp2/gpmc/gpmc_to_fifo.v
@@ -36,7 +36,7 @@
 ////////////////////////////////////////////////////////////////////////
 
 module gpmc_to_fifo
-  #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10)
+  #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10, parameter XFER_OFFSET = 2)
   (input [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input EM_CLK, input EM_WE,
    input clk, input reset, input clear, input arst,
    output [17:0] data_o, output src_rdy_o, input dst_rdy_i,
@@ -47,7 +47,7 @@ module gpmc_to_fifo
     reg gpmc_state;
     reg [15:0] vita_len;
     reg [ADDR_WIDTH:1] addr;
-    wire [ADDR_WIDTH:1] last_addr = {vita_len[ADDR_WIDTH-2:0], 1'b0} - 1'b1 + 2;
+    wire [ADDR_WIDTH:1] last_addr = {vita_len[ADDR_WIDTH-2:0], 1'b0} - 1'b1 + XFER_OFFSET;
     reg [PTR_WIDTH:0] gpmc_ptr, next_gpmc_ptr;
     localparam GPMC_STATE_START = 0;
     localparam GPMC_STATE_FILL = 1;
@@ -75,7 +75,7 @@ module gpmc_to_fifo
             case(gpmc_state)
 
             GPMC_STATE_START: begin
-                if (EM_A == 2) begin
+                if (EM_A == XFER_OFFSET) begin
                     gpmc_state <= GPMC_STATE_FILL;
                     vita_len <= EM_D;
                     next_gpmc_ptr <= gpmc_ptr + 1;
@@ -123,14 +123,14 @@ module gpmc_to_fifo
         if (reset | clear) begin
             fifo_state <= FIFO_STATE_CLAIM;
             fifo_ptr <= 0;
-            counter <= 2;
+            counter <= XFER_OFFSET;
         end
         else begin
             case(fifo_state)
 
             FIFO_STATE_CLAIM: begin
                 if (bram_available_to_empty && data_o[16]) fifo_state <= FIFO_STATE_PRE;
-                counter <= 2;
+                counter <= XFER_OFFSET;
             end
 
             FIFO_STATE_PRE: begin
@@ -142,7 +142,7 @@ module gpmc_to_fifo
                 if (src_rdy_o && dst_rdy_i && data_o[17]) begin
                     fifo_state <= FIFO_STATE_CLAIM;
                     fifo_ptr <= fifo_ptr + 1;
-                    counter <= 2;
+                    counter <= XFER_OFFSET;
                 end
                 else if (src_rdy_o && dst_rdy_i) begin
                     counter <= counter + 1;
@@ -159,7 +159,7 @@ module gpmc_to_fifo
 
     //assign data and frame bits to bram input
     assign data_i[15:0] = EM_D;
-    assign data_i[16] = (addr == 2);
+    assign data_i[16] = (addr == XFER_OFFSET);
     assign data_i[17] = (addr == last_addr);
 
     //instantiate dual ported bram for async read + write
diff --git a/usrp2/top/E1x0/E100.ucf b/usrp2/top/E1x0/E1x0.ucf
index 278fc289a..278fc289a 100644
--- a/usrp2/top/E1x0/E100.ucf
+++ b/usrp2/top/E1x0/E1x0.ucf
diff --git a/usrp2/top/E1x0/E100.v b/usrp2/top/E1x0/E1x0.v
index 080ae24c7..e7b0a4e00 100644
--- a/usrp2/top/E1x0/E100.v
+++ b/usrp2/top/E1x0/E1x0.v
@@ -18,7 +18,7 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 
-module E100
+module E1x0
   (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
    output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
    input debug_pb, output FPGA_TXD, input FPGA_RXD,
@@ -193,4 +193,4 @@ module E100
     //assign debug = gpmc_debug;
     assign debug = core_debug;
 
-endmodule // E100
+endmodule // E1x0
diff --git a/usrp2/top/E1x0/Makefile.E100 b/usrp2/top/E1x0/Makefile.E100
index 2b0ae8367..92334d987 100644
--- a/usrp2/top/E1x0/Makefile.E100
+++ b/usrp2/top/E1x0/Makefile.E100
@@ -5,7 +5,7 @@
 ##################################################
 # Project Setup
 ##################################################
-TOP_MODULE = E100
+TOP_MODULE = E1x0
 BUILD_DIR = $(abspath build$(ISE)-E100)
 
 # set me in a custom makefile
@@ -49,8 +49,8 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 ##################################################
 TOP_SRCS = \
 ../B100/u1plus_core.v \
-E100.v \
-E100.ucf \
+E1x0.v \
+E1x0.ucf \
 timing.ucf
 
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110
index 8de0714c3..e5be8d2fa 100644
--- a/usrp2/top/E1x0/Makefile.E110
+++ b/usrp2/top/E1x0/Makefile.E110
@@ -5,7 +5,7 @@
 ##################################################
 # Project Setup
 ##################################################
-TOP_MODULE = u1e
+TOP_MODULE = E1x0
 BUILD_DIR = $(abspath build$(ISE)-E110)
 
 # set me in a custom makefile
@@ -49,8 +49,8 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 ##################################################
 TOP_SRCS = \
 ../B100/u1plus_core.v \
-E100.v \
-E100.ucf \
+E1x0.v \
+E1x0.ucf \
 timing.ucf
 
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
diff --git a/usrp2/top/E1x0/timing.ucf b/usrp2/top/E1x0/timing.ucf
index 16f06dab7..6bd559426 100644
--- a/usrp2/top/E1x0/timing.ucf
+++ b/usrp2/top/E1x0/timing.ucf
@@ -14,7 +14,7 @@ INST "EM_NCS6" TNM = gpmc_net;
 INST "EM_NWE" TNM = gpmc_net;
 INST "EM_NOE" TNM = gpmc_net;
 
-TIMEGRP "gpmc_net" OFFSET = IN 5 ns VALID 10 ns BEFORE "EM_CLK" FALLING;
+TIMEGRP "gpmc_net" OFFSET = IN 7 ns VALID 14 ns BEFORE "EM_CLK" FALLING;
 TIMEGRP "gpmc_net_out" OFFSET = OUT 14 ns AFTER "EM_CLK" RISING; //2 clock cyc per read
 
 #constrain interrupt lines