usrp2: reg map change for GPIO core

5 files changed, 11 insertions, 9 deletions

diff --git a/host/lib/usrp/cores/gpio_core_200.cpp b/host/lib/usrp/cores/gpio_core_200.cpp
index 8639b1851..d756097ff 100644
--- a/host/lib/usrp/cores/gpio_core_200.cpp
+++ b/host/lib/usrp/cores/gpio_core_200.cpp
@@ -23,15 +23,14 @@
 #define REG_GPIO_TX_ONLY       _base + 8
 #define REG_GPIO_BOTH          _base + 12
 #define REG_GPIO_DDR           _base + 16
-#define REG_GPIO_READ          _base + 0 //any address will readback
 
 using namespace uhd;
 using namespace usrp;
 
 class gpio_core_200_impl : public gpio_core_200{
 public:
-    gpio_core_200_impl(wb_iface::sptr iface, const size_t base):
-        _iface(iface), _base(base) { /* NOP */ }
+    gpio_core_200_impl(wb_iface::sptr iface, const size_t base, const size_t rb_addr):
+        _iface(iface), _base(base), _rb_addr(rb_addr) { /* NOP */ }
 
     void set_pin_ctrl(const unit_t unit, const boost::uint16_t value){
         _pin_ctrl[unit] = value; //shadow
@@ -57,12 +56,13 @@ public:
     }
 
     boost::uint16_t read_gpio(const unit_t unit){
-        return boost::uint16_t(_iface->peek32(REG_GPIO_READ) >> unit2shit(unit));
+        return boost::uint16_t(_iface->peek32(_rb_addr) >> unit2shit(unit));
     }
 
 private:
     wb_iface::sptr _iface;
     const size_t _base;
+    const size_t _rb_addr;
 
     uhd::dict<unit_t, boost::uint16_t> _pin_ctrl, _gpio_out, _gpio_ddr;
     uhd::dict<unit_t, uhd::dict<atr_reg_t, boost::uint16_t> > _atr_regs;
@@ -95,6 +95,6 @@ private:
 
 };
 
-gpio_core_200::sptr gpio_core_200::make(wb_iface::sptr iface, const size_t base){
-    return sptr(new gpio_core_200_impl(iface, base));
+gpio_core_200::sptr gpio_core_200::make(wb_iface::sptr iface, const size_t base, const size_t rb_addr){
+    return sptr(new gpio_core_200_impl(iface, base, rb_addr));
 }
diff --git a/host/lib/usrp/cores/gpio_core_200.hpp b/host/lib/usrp/cores/gpio_core_200.hpp
index 7ff2af649..278575874 100644
--- a/host/lib/usrp/cores/gpio_core_200.hpp
+++ b/host/lib/usrp/cores/gpio_core_200.hpp
@@ -33,7 +33,7 @@ public:
     typedef uhd::usrp::dboard_iface::atr_reg_t atr_reg_t;
 
     //! makes a new GPIO core from iface and slave base
-    static sptr make(wb_iface::sptr iface, const size_t base);
+    static sptr make(wb_iface::sptr iface, const size_t base, const size_t rb_addr);
 
     //! 1 = ATR
     virtual void set_pin_ctrl(const unit_t unit, const boost::uint16_t value) = 0;
diff --git a/host/lib/usrp/usrp2/dboard_iface.cpp b/host/lib/usrp/usrp2/dboard_iface.cpp
index c31fc52b7..bc510c8a1 100644
--- a/host/lib/usrp/usrp2/dboard_iface.cpp
+++ b/host/lib/usrp/usrp2/dboard_iface.cpp
@@ -107,7 +107,7 @@ usrp2_dboard_iface::usrp2_dboard_iface(
 ){
     _iface = iface;
     _clock_ctrl = clock_ctrl;
-    _gpio = gpio_core_200::make(_iface, GPIO_BASE);
+    _gpio = gpio_core_200::make(_iface, U2_REG_SR_ADDR(SR_GPIO), U2_REG_GPIO_RB);
 
     //reset the aux dacs
     _dac_regs[UNIT_RX] = ad5623_regs_t();
diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h
index 7ad06f33f..62ba2d792 100644
--- a/host/lib/usrp/usrp2/fw_common.h
+++ b/host/lib/usrp/usrp2/fw_common.h
@@ -30,7 +30,7 @@ extern "C" {
 #endif
 
 //fpga and firmware compatibility numbers
-#define USRP2_FPGA_COMPAT_NUM 7
+#define USRP2_FPGA_COMPAT_NUM 8
 #define USRP2_FW_COMPAT_NUM 11
 #define USRP2_FW_VER_MINOR 0
 
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 8839997f1..179a930c6 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -50,6 +50,7 @@
 #define SR_TX_CTRL  144   // 6
 #define SR_TX_DSP   160   // 5
 
+#define SR_GPIO     184
 #define SR_UDP_SM   192   // 64
 
 #define U2_REG_SR_ADDR(sr) (SETTING_REGS_BASE + (4 * (sr)))
@@ -95,6 +96,7 @@
 // Readback regs
 ////////////////////////////////////////////////
 #define U2_REG_STATUS READBACK_BASE + 4*8
+#define U2_REG_GPIO_RB READBACK_BASE + 4*9
 #define U2_REG_TIME64_SECS_RB_IMM READBACK_BASE + 4*10
 #define U2_REG_TIME64_TICKS_RB_IMM READBACK_BASE + 4*11
 #define U2_REG_COMPAT_NUM_RB READBACK_BASE + 4*12