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| author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-03-29 15:35:06 -0700 |
|---|---|---|
| committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-03-29 15:35:06 -0700 |
| commit | 50b1ca13e651152a731d3fdf7a5f532b65e04e13 (patch) | |
| tree | 6f70f0fd06a53cec4d65be384f437997caada5a4 | |
| parent | 5642e3be330b707254625de7ce33fa219edf0ab9 (diff) | |
| download | uhd-50b1ca13e651152a731d3fdf7a5f532b65e04e13.tar.gz uhd-50b1ca13e651152a731d3fdf7a5f532b65e04e13.tar.bz2 uhd-50b1ca13e651152a731d3fdf7a5f532b65e04e13.zip | |
Added timing constraint for Wishbone clock/dsp_clock skew
| -rw-r--r-- | usrp2/top/u2_rev3/u2_rev3.ucf | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf index 255a298ac..6aa699d2a 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -331,3 +331,5 @@ NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; #NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; #NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; |