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authorJosh Blum <josh@joshknows.com>2010-08-09 16:56:53 -0700
committerJosh Blum <josh@joshknows.com>2010-08-09 16:56:53 -0700
commit349d99c988b2eeb3d13d6229cbd4b80bc9f8153a (patch)
tree1c902bf9199f9f131987e6dec42156c56f481eea
parent55658336cf67810ab8cd7829b9a1fa86c8cd4539 (diff)
parentc174bf9acb2b2d142456f1186bd3e41e40d8a6d1 (diff)
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Merge branch 'features' into uhd_fpga_features
Conflicts: fpga/usrp2/vrt/vita_rx_control.v
Diffstat
-rw-r--r--fpga/usrp2/control_lib/Makefile.srcs1
-rw-r--r--fpga/usrp2/control_lib/ram_harvard.v69
-rw-r--r--fpga/usrp2/control_lib/ram_loader.v460
-rw-r--r--fpga/usrp2/fifo/Makefile.srcs2
-rw-r--r--fpga/usrp2/fifo/fifo36_demux.v50
-rw-r--r--fpga/usrp2/fifo/fifo36_mux.v57
-rw-r--r--fpga/usrp2/fifo/fifo_new_tb.vcd5506
-rw-r--r--fpga/usrp2/fifo/fifo_tb.v25
-rw-r--r--fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v5
-rw-r--r--fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v27
-rw-r--r--fpga/usrp2/sdr_lib/dsp_core_tx.v4
-rwxr-xr-x[-rw-r--r--]fpga/usrp2/top/u2_rev3/u2_core.v50
-rw-r--r--fpga/usrp2/top/u2_rev3/u2_core_udp.v119
-rw-r--r--fpga/usrp2/udp/prot_eng_tx.v19
-rw-r--r--fpga/usrp2/vrt/Makefile.srcs2
-rw-r--r--fpga/usrp2/vrt/gen_context_pkt.v72
-rwxr-xr-xfpga/usrp2/vrt/vita_rx.build2
-rw-r--r--fpga/usrp2/vrt/vita_rx_control.v5
-rw-r--r--fpga/usrp2/vrt/vita_rx_framer.v47
-rw-r--r--fpga/usrp2/vrt/vita_rx_tb.v11
-rw-r--r--fpga/usrp2/vrt/vita_tx_chain.v71
-rw-r--r--fpga/usrp2/vrt/vita_tx_control.v115
-rw-r--r--fpga/usrp2/vrt/vita_tx_deframer.v32
23 files changed, 873 insertions, 5878 deletions
diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs
index 5e2a96a53..bc8e4d5bc 100644
--- a/fpga/usrp2/control_lib/Makefile.srcs
+++ b/fpga/usrp2/control_lib/Makefile.srcs
@@ -20,6 +20,7 @@ mux8.v \
nsgpio.v \
ram_2port.v \
ram_harv_cache.v \
+ram_harvard.v \
ram_loader.v \
setting_reg.v \
settings_bus.v \
diff --git a/fpga/usrp2/control_lib/ram_harvard.v b/fpga/usrp2/control_lib/ram_harvard.v
new file mode 100644
index 000000000..948f9b36f
--- /dev/null
+++ b/fpga/usrp2/control_lib/ram_harvard.v
@@ -0,0 +1,69 @@
+
+
+// Dual ported, Harvard architecture, cached ram
+
+module ram_harvard
+ #(parameter AWIDTH=15,
+ parameter RAM_SIZE=16384,
+ parameter ICWIDTH=6,
+ parameter DCWIDTH=6)
+
+ (input wb_clk_i,
+ input wb_rst_i,
+ // Firmware download port.
+ input [AWIDTH-1:0] ram_loader_adr_i,
+ input [31:0] ram_loader_dat_i,
+ input [3:0] ram_loader_sel_i,
+ input ram_loader_stb_i,
+ input ram_loader_we_i,
+ input ram_loader_done_i,
+ // Instruction fetch port.
+ input [AWIDTH-1:0] if_adr,
+ output [31:0] if_data,
+ // Data access port.
+ input [AWIDTH-1:0] dwb_adr_i,
+ input [31:0] dwb_dat_i,
+ output [31:0] dwb_dat_o,
+ input dwb_we_i,
+ output dwb_ack_o,
+ input dwb_stb_i,
+ input [3:0] dwb_sel_i,
+
+ input flush_icache );
+
+ reg ack_d1;
+ reg stb_d1;
+
+ dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE))
+ sys_ram
+ (.clk(wb_clk_i),
+ .adr1_i(ram_loader_done_i ? if_adr : ram_loader_adr_i),
+ .dat1_i(ram_loader_dat_i),
+ .dat1_o(if_data),
+ .we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i),
+ .en1_i(ram_loader_done_i ? 1'b1 : ram_loader_stb_i),
+ //.sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i),
+ .sel1_i(ram_loader_sel_i), // Sel is only for writes anyway
+ .adr2_i(dwb_adr_i),
+ .dat2_i(dwb_dat_i),
+ .dat2_o(dwb_dat_o),
+ .we2_i(dwb_we_i),
+ .en2_i(dwb_stb_i),
+ .sel2_i(dwb_sel_i)
+ );
+
+ assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
+
+ always @(posedge wb_clk_i)
+ if(wb_rst_i)
+ ack_d1 <= 1'b0;
+ else
+ ack_d1 <= dwb_ack_o;
+
+ always @(posedge wb_clk_i)
+ if(wb_rst_i)
+ stb_d1 <= 0;
+ else
+ stb_d1 <= dwb_stb_i;
+
+endmodule // ram_harvard
diff --git a/fpga/usrp2/control_lib/ram_loader.v b/fpga/usrp2/control_lib/ram_loader.v
index cb67de739..c53ea7aa7 100644
--- a/fpga/usrp2/control_lib/ram_loader.v
+++ b/fpga/usrp2/control_lib/ram_loader.v
@@ -1,225 +1,261 @@
+module ram_loader
+ #(parameter AWIDTH=16, RAM_SIZE=16384)
+ (
+ // Wishbone I/F and clock domain
+ input wb_clk,
+ input dsp_clk,
+ input ram_loader_rst,
+ output wire [31:0] wb_dat,
+ output wire [AWIDTH-1:0] wb_adr,
+ output wb_stb,
+ output reg [3:0] wb_sel,
+ output wb_we,
+ output reg ram_loader_done,
+ // CPLD signals and clock domain
+ input cpld_clk,
+ input cpld_din,
+ output reg cpld_start,
+ output reg cpld_mode,
+ output reg cpld_done,
+ input cpld_detached
+ );
-// Adapted from VHDL code in spi_boot by Arnim Legauer
-// Added a full wishbone master interface (32-bit)
-
-module ram_loader #(parameter AWIDTH=16, RAM_SIZE=16384)
- (input clk_i, input rst_i,
- // CPLD Interface
- input cfg_clk_i, input cfg_data_i,
- output start_o, output mode_o, output done_o,
- input detached_i,
- // Wishbone interface
- output wire [31:0] wb_dat_o,
- output reg [AWIDTH-1:0] wb_adr_o,
- output wb_stb_o,
- output wb_cyc_o,
- output reg [3:0] wb_sel_o,
- output reg wb_we_o,
- input wb_ack_i,
- output ram_loader_done_o);
+ localparam S0 = 0;
+ localparam S1 = 1;
+ localparam S2 = 2;
+ localparam S3 = 3;
+ localparam S4 = 4;
+ localparam S5 = 5;
+ localparam S6 = 6;
+ localparam RESET = 7;
- // FSM to control start signal, clocked on main clock
- localparam FSM1_WAIT_DETACH = 2'b00;
- localparam FSM1_CHECK_NO_DONE = 2'b01;
- localparam FSM1_WAIT_DONE = 2'b10;
-
- reg [1:0] start_fsm_q, start_fsm_s;
- reg start_q, enable_q, start_s, enable_s;
- reg done_q, done_s;
+ localparam WB_IDLE = 0;
+ localparam WB_WRITE = 1;
+
+
+ reg [AWIDTH+2:0] count; // 3 LSB's count bits in, the MSB's generate the Wishbone address
+ reg [6:0] shift_reg;
+ reg [7:0] data_reg;
+ reg sampled_clk;
+ reg sampled_clk_meta;
+ reg sampled_din;
+ reg inc_count;
+ reg load_data_reg;
+ reg shift;
+ reg wb_state, wb_next_state;
+ reg [2:0] state, next_state;
+
+ //
+ // CPLD clock doesn't free run and is approximately 12.5MHz.
+ // Use 50MHz Wishbone clock to sample it as a signal and avoid having
+ // an extra clock domain for no reason.
+ //
+
+ always @(posedge dsp_clk or posedge ram_loader_rst)
+ if (ram_loader_rst)
+ begin
+ sampled_clk_meta <= 1'b0;
+ sampled_clk <= 1'b0;
+ sampled_din <= 1'b0;
+ count <= 'h7FFF8; // Initialize so that address will be 0 when first byte fully received.
+ data_reg <= 0;
+ shift_reg <= 0;
+ end
+ else
+ begin
+ sampled_clk_meta <= cpld_clk;
+ sampled_clk <= sampled_clk_meta;
+ sampled_din <= cpld_din;
+ if (inc_count)
+ count <= count + 1'b1;
+ if (load_data_reg)
+ data_reg <= {shift_reg,sampled_din};
+ if (shift)
+ shift_reg <= {shift_reg[5:0],sampled_din};
+ end // else: !if(ram_loader_rst)
- always @(posedge clk_i or posedge rst_i)
- if(rst_i)
- begin
- start_fsm_q <= FSM1_WAIT_DETACH;
- start_q <= 1'b0;
- enable_q <= 1'b0;
- end
+
+ always @(posedge dsp_clk or posedge ram_loader_rst)
+ if (ram_loader_rst)
+ state <= RESET;
else
- begin
- start_fsm_q <= start_fsm_s;
- enable_q <= enable_s;
- start_q <= start_s;
- end // else: !if(rst_i)
-
+ state <= next_state;
+
+
always @*
- case(start_fsm_q)
- FSM1_WAIT_DETACH:
- if(detached_i == 1'b1)
- begin
- start_fsm_s <= FSM1_CHECK_NO_DONE;
- enable_s <= 1'b1;
- start_s <= 1'b1;
- end
- else
- begin
- start_fsm_s <= FSM1_WAIT_DETACH;
- enable_s <= enable_q;
- start_s <= start_q;
- end // else: !if(detached_i == 1'b1)
- FSM1_CHECK_NO_DONE:
- if(~done_q)
- begin
- start_fsm_s <= FSM1_WAIT_DONE;
- enable_s <= enable_q;
- start_s <= start_q;
- end
- else
- begin
- start_fsm_s <= FSM1_CHECK_NO_DONE;
- enable_s <= enable_q;
- start_s <= start_q;
- end // else: !if(~done_q)
- FSM1_WAIT_DONE:
- if(done_q)
- begin
- start_fsm_s <= FSM1_WAIT_DETACH;
- enable_s <= 1'b0;
- start_s <= 1'b0;
- end
- else
- begin
- start_fsm_s <= FSM1_WAIT_DONE;
- enable_s <= enable_q;
- start_s <= start_q;
- end // else: !if(done_q)
- default:
- begin
- start_fsm_s <= FSM1_WAIT_DETACH;
- enable_s <= enable_q;
- start_s <= start_q;
- end // else: !if(done_q)
- endcase // case(start_fsm_q)
-
- // FSM running on data clock
-
- localparam FSM2_IDLE = 3'b000;
- localparam FSM2_WE_ON = 3'b001;
- localparam FSM2_WE_OFF = 3'b010;
- localparam FSM2_INC_ADDR1 = 3'b011;
- localparam FSM2_INC_ADDR2 = 3'b100;
- localparam FSM2_FINISHED = 3'b101;
-
- reg [AWIDTH-1:0] addr_q;
- reg [7:0] shift_dat_q, ser_dat_q;
- reg [2:0] bit_q, fsm_q, fsm_s;
- reg bit_ovfl_q, ram_we_s, ram_we_q, mode_q, mode_s, inc_addr_s;
-
- always @(posedge cfg_clk_i or posedge rst_i)
- if(rst_i)
- begin
- addr_q <= 0;
- shift_dat_q <= 8'd0;
- ser_dat_q <= 8'd0;
- bit_q <= 3'd0;
- bit_ovfl_q <= 1'b0;
- fsm_q <= FSM2_IDLE;
- ram_we_q <= 1'b0;
- done_q <= 1'b0;
- mode_q <= 1'b0;
- end
+ begin
+ // Defaults
+ next_state = state;
+ cpld_start = 1'b0;
+ shift = 1'b0;
+ inc_count = 0;
+ load_data_reg = 1'b0;
+ ram_loader_done = 1'b0;
+ cpld_mode = 1'b0;
+ cpld_done = 1'b1;
+
+
+
+ case (state) //synthesis parallel_case full_case
+ // After reset wait until CPLD indicates its detached.
+ RESET: begin
+ if (cpld_detached)
+ next_state = S0;
+ else
+ next_state = RESET;
+ end
+
+ // Assert cpld_start to signal the CPLD its to start sending serial clock and data.
+ // Assume cpld_clk is low as we transition into search for first rising edge
+ S0: begin
+ cpld_start = 1'b1;
+ cpld_done = 1'b0;
+ if (~cpld_detached)
+ next_state = S2;
+ else
+ next_state = S0;
+ end
+
+ //
+ S1: begin
+ cpld_start = 1'b1;
+ cpld_done = 1'b0;
+ if (sampled_clk)
+ begin
+ // Found rising edge on cpld_clk.
+ if (count[2:0] == 3'b111)
+ // Its the last bit of a byte, send it out to the Wishbone bus.
+ begin
+ load_data_reg = 1'b1;
+ inc_count = 1'b1;
+ end
+ else
+ // Shift databit into LSB of shift register and increment count
+ begin
+ shift = 1'b1;
+ inc_count = 1'b1;
+ end // else: !if(count[2:0] == 3'b111)
+ next_state = S2;
+ end // if (sampled_clk)
+ else
+ next_state = S1;
+ end // case: S1
+
+ //
+ S2: begin
+ cpld_start = 1'b1;
+ cpld_done = 1'b0;
+ if (~sampled_clk)
+ // Found negative edge of clock
+ if (count[AWIDTH+2:3] == RAM_SIZE-1) // NOTE need to change this constant
+ // All firmware now downloaded
+ next_state = S3;
+ else
+ next_state = S1;
+ else
+ next_state = S2;
+ end // case: S2
+
+ // Now that terminal count is reached and all firmware is downloaded signal CPLD that download is done
+ // and that mode is now SPI mode.
+ S3: begin
+ if (sampled_clk)
+ begin
+ cpld_mode = 1'b1;
+ cpld_done = 1'b1;
+ next_state = S4;
+ end
+ else
+ next_state = S3;
+ end
+
+ // Search for negedge of cpld_clk whilst keeping done sequence asserted.
+ // Keep done assserted
+ S4: begin
+ cpld_mode = 1'b1;
+ cpld_done = 1'b1;
+ if (~sampled_clk)
+ next_state = S5;
+ else
+ next_state = S4;
+ end
+
+ // Search for posedge of cpld_clk whilst keeping done sequence asserted.
+ S5: begin
+ cpld_mode = 1'b1;
+ cpld_done = 1'b1;
+ if (sampled_clk)
+ next_state = S6;
+ else
+ next_state = S5;
+ end
+
+ // Stay in this state until reset/power down
+ S6: begin
+ ram_loader_done = 1'b1;
+ cpld_done = 1'b1;
+ cpld_mode = 1'b1;
+ next_state = S6;
+ end
+
+ endcase // case(state)
+ end
+
+ always @(posedge dsp_clk or posedge ram_loader_rst)
+ if (ram_loader_rst)
+ wb_state <= WB_IDLE;
else
- begin
- if(inc_addr_s)
- addr_q <= addr_q + 1;
- if(enable_q)
- begin
- bit_q <= bit_q + 1;
- bit_ovfl_q <= (bit_q == 3'd7);
- shift_dat_q[0] <= cfg_data_i;
- shift_dat_q[7:1] <= shift_dat_q[6:0];
- end
- if(bit_ovfl_q)
- ser_dat_q <= shift_dat_q;
-
- fsm_q <= fsm_s;
-
- ram_we_q <= ram_we_s;
-
- if(done_s)
- done_q <= 1'b1;
- mode_q <= mode_s;
- end // else: !if(rst_i)
+ wb_state <= wb_next_state;
+ reg do_write;
+ wire empty, full;
+
always @*
begin
- inc_addr_s <= 1'b0;
- ram_we_s <= 1'b0;
- done_s <= 1'b0;
- fsm_s <= FSM2_IDLE;
- mode_s <= 1'b0;
-
- case(fsm_q)
- FSM2_IDLE :
- if(start_q)
- if(bit_ovfl_q)
- fsm_s <= FSM2_WE_ON;
- FSM2_WE_ON:
- begin
- ram_we_s <= 1'b1;
- fsm_s <= FSM2_WE_OFF;
- end
- FSM2_WE_OFF:
- begin
- ram_we_s <= 1'b1;
- fsm_s <= FSM2_INC_ADDR1;
- end
- FSM2_INC_ADDR1:
- fsm_s <= FSM2_INC_ADDR2;
- FSM2_INC_ADDR2:
- if(addr_q == (RAM_SIZE-1))
- //if(&addr_q)
- begin
- fsm_s <= FSM2_FINISHED;
- done_s <= 1'b1;
- mode_s <= 1'b1;
- end
- else
- begin
- inc_addr_s <= 1'b1;
- fsm_s <= FSM2_IDLE;
- end // else: !if(&addr_q)
- FSM2_FINISHED:
- begin
- fsm_s <= FSM2_FINISHED;
- mode_s <= 1'b1;
- end
- endcase // case(fsm_q)
+ wb_next_state = wb_state;
+ do_write = 1'b0;
+
+ case (wb_state) //synthesis full_case parallel_case
+ //
+ WB_IDLE: begin
+ if (load_data_reg)
+ // Data reg will load ready to write wishbone @ next clock edge
+ wb_next_state = WB_WRITE;
+ else
+ wb_next_state = WB_IDLE;
+ end
+
+ // Drive address and data onto wishbone.
+ WB_WRITE: begin
+ do_write = 1'b1;
+ if (~full)
+ wb_next_state = WB_IDLE;
+ else
+ wb_next_state = WB_WRITE;
+ end
+
+ endcase // case(wb_state)
end // always @ *
- assign start_o = start_q;
- assign mode_o = mode_q;
- assign done_o = start_q ? done_q : 1'b1;
- wire [AWIDTH-1:0] ram_addr = addr_q;
- wire [7:0] ram_data = ser_dat_q;
- assign ram_loader_done_o = (fsm_q == FSM2_FINISHED);
-
- // wishbone master, only writes
- reg [7:0] dat_holder;
- assign wb_dat_o = {4{dat_holder}};
- assign wb_stb_o = wb_we_o;
- assign wb_cyc_o = wb_we_o;
+ wire [1:0] count_out;
+ wire [7:0] data_out;
+
+ fifo_xlnx_16x40_2clk crossclk
+ (.rst(ram_loader_rst),
+ .wr_clk(dsp_clk), .din({count[4:3],count[AWIDTH+2:3],data_reg}), .wr_en(do_write), .full(full),
+ .rd_clk(wb_clk), .dout({count_out,wb_adr,data_out}), .rd_en(~empty), .empty(empty));
+
+ assign wb_dat = {4{data_out}};
+
+ always @*
+ case(count_out[1:0]) //synthesis parallel_case full_case
+ 2'b00 : wb_sel = 4'b1000;
+ 2'b01 : wb_sel = 4'b0100;
+ 2'b10 : wb_sel = 4'b0010;
+ 2'b11 : wb_sel = 4'b0001;
+ endcase
+
+ assign wb_we = ~empty;
+ assign wb_stb = ~empty;
- always @(posedge clk_i or posedge rst_i)
- if(rst_i)
- begin
- dat_holder <= 8'd0;
- wb_adr_o <= 0;
- wb_sel_o <= 4'b0000;
- wb_we_o <= 1'b0;
- end
- else if(ram_we_q)
- begin
- dat_holder <= ram_data;
- wb_adr_o <= ram_addr;
- wb_we_o <= 1'b1;
- case(ram_addr[1:0]) // Big Endian
- 2'b00 : wb_sel_o <= 4'b1000;
- 2'b01 : wb_sel_o <= 4'b0100;
- 2'b10 : wb_sel_o <= 4'b0010;
- 2'b11 : wb_sel_o <= 4'b0001;
- endcase // case(ram_addr[1:0])
- end // if (ram_we_q)
- else if(wb_ack_i)
- wb_we_o <= 1'b0;
-
endmodule // ram_loader
diff --git a/fpga/usrp2/fifo/Makefile.srcs b/fpga/usrp2/fifo/Makefile.srcs
index 22867da7e..c66979132 100644
--- a/fpga/usrp2/fifo/Makefile.srcs
+++ b/fpga/usrp2/fifo/Makefile.srcs
@@ -20,4 +20,6 @@ fifo19_to_ll8.v \
ll8_to_fifo19.v \
fifo36_to_fifo19.v \
fifo19_to_fifo36.v \
+fifo36_mux.v \
+fifo36_demux.v \
))
diff --git a/fpga/usrp2/fifo/fifo36_demux.v b/fpga/usrp2/fifo/fifo36_demux.v
new file mode 100644
index 000000000..a54759d4d
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo36_demux.v
@@ -0,0 +1,50 @@
+
+// Demux packets from a fifo based on the contents of the first line
+// If first line matches the parameter and mask, send to data1, otherwise send to data0
+
+module fifo36_demux
+ #(parameter match_data = 0,
+ parameter match_mask = 0)
+ (input clk, input reset, input clear,
+ input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+ output [35:0] data0_o, output src0_rdy_o, input dst0_rdy_i,
+ output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i);
+
+ localparam DMX_IDLE = 0;
+ localparam DMX_DATA0 = 1;
+ localparam DMX_DATA1 = 2;
+
+ reg [1:0] state;
+
+ wire match = |( (data_i ^ match_data) & match_mask );
+ wire eof = data_i[33];
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= DMX_IDLE;
+ else
+ case(state)
+ DMX_IDLE :
+ if(src_rdy_i)
+ if(match)
+ state <= DMX_DATA1;
+ else
+ state <= DMX_DATA0;
+ DMX_DATA0 :
+ if(src_rdy_i & dst0_rdy_i & eof)
+ state <= DMX_IDLE;
+ DMX_DATA1 :
+ if(src_rdy_i & dst1_rdy_i & eof)
+ state <= DMX_IDLE;
+ default :
+ state <= DMX_IDLE;
+ endcase // case (state)
+
+ assign dst_rdy_o = (state==DMX_IDLE) ? 0 : (state==DMX_DATA0) ? dst0_rdy_i : dst1_rdy_i;
+ assign src0_rdy_o = (state==DMX_DATA0) ? src_rdy_i : 0;
+ assign src1_rdy_o = (state==DMX_DATA1) ? src_rdy_i : 0;
+
+ assign data0_o = data_i;
+ assign data1_o = data_i;
+
+endmodule // fifo36_demux
diff --git a/fpga/usrp2/fifo/fifo36_mux.v b/fpga/usrp2/fifo/fifo36_mux.v
new file mode 100644
index 000000000..92bf13ff9
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo36_mux.v
@@ -0,0 +1,57 @@
+
+// Mux packets from multiple FIFO interfaces onto a single one.
+// Can alternate or give priority to one port (port 0)
+// In prio mode, port 1 will never get access if port 0 is always busy
+
+module fifo36_mux
+ #(parameter prio = 0)
+ (input clk, input reset, input clear,
+ input [35:0] data0_i, input src0_rdy_i, output dst0_rdy_o,
+ input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
+ output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+ localparam MUX_IDLE0 = 0;
+ localparam MUX_DATA0 = 1;
+ localparam MUX_IDLE1 = 2;
+ localparam MUX_DATA1 = 3;
+
+ reg [1:0] state;
+
+ wire eof0 = data0_i[33];
+ wire eof1 = data1_i[33];
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= MUX_IDLE0;
+ else
+ case(state)
+ MUX_IDLE0 :
+ if(src0_rdy_i)
+ state <= MUX_DATA0;
+ else if(src1_rdy_i)
+ state <= MUX_DATA1;
+
+ MUX_DATA0 :
+ if(src0_rdy_i & dst_rdy_i & eof0)
+ state <= prio ? MUX_IDLE0 : MUX_IDLE1;
+
+ MUX_IDLE1 :
+ if(src1_rdy_i)
+ state <= MUX_DATA1;
+ else if(src0_rdy_i)
+ state <= MUX_DATA0;
+
+ MUX_DATA1 :
+ if(src1_rdy_i & dst_rdy_i & eof1)
+ state <= MUX_IDLE0;
+
+ default :
+ state <= MUX_IDLE0;
+ endcase // case (state)
+
+ assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0;
+ assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0;
+ assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0;
+ assign data_o = (state==MUX_DATA0) ? data0_i : data1_i;
+
+endmodule // fifo36_demux
diff --git a/fpga/usrp2/fifo/fifo_new_tb.vcd b/fpga/usrp2/fifo/fifo_new_tb.vcd
deleted file mode 100644
index 796889e7d..000000000
--- a/fpga/usrp2/fifo/fifo_new_tb.vcd
+++ /dev/null
@@ -1,5506 +0,0 @@
-$date
- Thu Mar 19 17:21:11 2009
-$end
-$version
- Icarus Verilog
-$end
-$timescale
- 1ps
-$end
-$scope module fifo_new_tb $end
-$var wire 1 ! dst_rdy_f36i $end
-$var wire 36 " f36_in [35:0] $end
-$var wire 36 # i1 [35:0] $end
-$var wire 1 $ i1_dr $end
-$var wire 1 % i1_sr $end
-$var wire 19 & i2 [18:0] $end
-$var wire 1 ' i2_dr $end
-$var wire 1 ( i2_sr $end
-$var wire 19 ) i3 [18:0] $end
-$var wire 1 * i3_dr $end
-$var wire 1 + i3_sr $end
-$var wire 36 , i4 [35:0] $end
-$var wire 1 - i4_sr $end
-$var wire 8 . ll_data [7:0] $end
-$var wire 1 / ll_dst_rdy_n $end
-$var wire 1 0 ll_eof_n $end
-$var wire 1 1 ll_sof_n $end
-$var wire 1 2 ll_src_rdy_n $end
-$var reg 1 3 clear $end
-$var reg 1 4 clk $end
-$var reg 16 5 count [15:0] $end
-$var reg 1 6 dst_rdy_f36o $end
-$var reg 32 7 f36_data [31:0] $end
-$var reg 1 8 f36_eof $end
-$var reg 2 9 f36_occ [1:0] $end
-$var reg 1 : f36_sof $end
-$var reg 1 ; i4_dr $end
-$var reg 1 < rst $end
-$var reg 1 = src_rdy_f36i $end
-$scope module fifo_short1 $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 36 @ datain [35:0] $end
-$var wire 36 A dataout [35:0] $end
-$var wire 1 $ dst_rdy_i $end
-$var wire 1 ! dst_rdy_o $end
-$var wire 1 B read $end
-$var wire 1 C reset $end
-$var wire 1 D src_rdy_i $end
-$var wire 1 % src_rdy_o $end
-$var wire 1 E write $end
-$var reg 4 F a [3:0] $end
-$var reg 1 G empty $end
-$var reg 1 H full $end
-$var reg 5 I occupied [4:0] $end
-$var reg 5 J space [4:0] $end
-$scope begin gen_srl16[0] $end
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-$var wire 1 K A0 $end
-$var wire 1 L A1 $end
-$var wire 1 M A2 $end
-$var wire 1 N A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 O D $end
-$var wire 1 P Q $end
-$var reg 16 Q data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[1] $end
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-$var wire 1 R A0 $end
-$var wire 1 S A1 $end
-$var wire 1 T A2 $end
-$var wire 1 U A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 V D $end
-$var wire 1 W Q $end
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-$var wire 1 Z A1 $end
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-$upscope $end
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-$scope begin gen_srl16[4] $end
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-$var wire 1 h A1 $end
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-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 k D $end
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-$upscope $end
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-$var wire 1 E CE $end
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-$scope begin gen_srl16[6] $end
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-$var wire 1 u A0 $end
-$var wire 1 v A1 $end
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-$var wire 1 E CE $end
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-$var wire 1 y D $end
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-$scope begin gen_srl16[7] $end
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-$var wire 1 } A1 $end
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-$var wire 1 !" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 "" D $end
-$var wire 1 #" Q $end
-$var reg 16 $" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[8] $end
-$scope module srl16e $end
-$var wire 1 %" A0 $end
-$var wire 1 &" A1 $end
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-$var wire 1 (" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 )" D $end
-$var wire 1 *" Q $end
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-$scope begin gen_srl16[9] $end
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-$var wire 1 ," A0 $end
-$var wire 1 -" A1 $end
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-$scope begin gen_srl16[10] $end
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-$var wire 1 6" A3 $end
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-$var wire 1 7" D $end
-$var wire 1 8" Q $end
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-$scope begin gen_srl16[11] $end
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-$var wire 1 :" A0 $end
-$var wire 1 ;" A1 $end
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-$var wire 1 =" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 >" D $end
-$var wire 1 ?" Q $end
-$var reg 16 @" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[12] $end
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-$var wire 1 A" A0 $end
-$var wire 1 B" A1 $end
-$var wire 1 C" A2 $end
-$var wire 1 D" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 E" D $end
-$var wire 1 F" Q $end
-$var reg 16 G" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[13] $end
-$scope module srl16e $end
-$var wire 1 H" A0 $end
-$var wire 1 I" A1 $end
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-$var wire 1 K" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 L" D $end
-$var wire 1 M" Q $end
-$var reg 16 N" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[14] $end
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-$var wire 1 O" A0 $end
-$var wire 1 P" A1 $end
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-$var wire 1 R" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 S" D $end
-$var wire 1 T" Q $end
-$var reg 16 U" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[15] $end
-$scope module srl16e $end
-$var wire 1 V" A0 $end
-$var wire 1 W" A1 $end
-$var wire 1 X" A2 $end
-$var wire 1 Y" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 Z" D $end
-$var wire 1 [" Q $end
-$var reg 16 \" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[16] $end
-$scope module srl16e $end
-$var wire 1 ]" A0 $end
-$var wire 1 ^" A1 $end
-$var wire 1 _" A2 $end
-$var wire 1 `" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 a" D $end
-$var wire 1 b" Q $end
-$var reg 16 c" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[17] $end
-$scope module srl16e $end
-$var wire 1 d" A0 $end
-$var wire 1 e" A1 $end
-$var wire 1 f" A2 $end
-$var wire 1 g" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 h" D $end
-$var wire 1 i" Q $end
-$var reg 16 j" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[18] $end
-$scope module srl16e $end
-$var wire 1 k" A0 $end
-$var wire 1 l" A1 $end
-$var wire 1 m" A2 $end
-$var wire 1 n" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 o" D $end
-$var wire 1 p" Q $end
-$var reg 16 q" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[19] $end
-$scope module srl16e $end
-$var wire 1 r" A0 $end
-$var wire 1 s" A1 $end
-$var wire 1 t" A2 $end
-$var wire 1 u" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 v" D $end
-$var wire 1 w" Q $end
-$var reg 16 x" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[20] $end
-$scope module srl16e $end
-$var wire 1 y" A0 $end
-$var wire 1 z" A1 $end
-$var wire 1 {" A2 $end
-$var wire 1 |" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 }" D $end
-$var wire 1 ~" Q $end
-$var reg 16 !# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[21] $end
-$scope module srl16e $end
-$var wire 1 "# A0 $end
-$var wire 1 ## A1 $end
-$var wire 1 $# A2 $end
-$var wire 1 %# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 &# D $end
-$var wire 1 '# Q $end
-$var reg 16 (# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[22] $end
-$scope module srl16e $end
-$var wire 1 )# A0 $end
-$var wire 1 *# A1 $end
-$var wire 1 +# A2 $end
-$var wire 1 ,# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 -# D $end
-$var wire 1 .# Q $end
-$var reg 16 /# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[23] $end
-$scope module srl16e $end
-$var wire 1 0# A0 $end
-$var wire 1 1# A1 $end
-$var wire 1 2# A2 $end
-$var wire 1 3# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 4# D $end
-$var wire 1 5# Q $end
-$var reg 16 6# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[24] $end
-$scope module srl16e $end
-$var wire 1 7# A0 $end
-$var wire 1 8# A1 $end
-$var wire 1 9# A2 $end
-$var wire 1 :# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 ;# D $end
-$var wire 1 <# Q $end
-$var reg 16 =# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[25] $end
-$scope module srl16e $end
-$var wire 1 ># A0 $end
-$var wire 1 ?# A1 $end
-$var wire 1 @# A2 $end
-$var wire 1 A# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 B# D $end
-$var wire 1 C# Q $end
-$var reg 16 D# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[26] $end
-$scope module srl16e $end
-$var wire 1 E# A0 $end
-$var wire 1 F# A1 $end
-$var wire 1 G# A2 $end
-$var wire 1 H# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 I# D $end
-$var wire 1 J# Q $end
-$var reg 16 K# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[27] $end
-$scope module srl16e $end
-$var wire 1 L# A0 $end
-$var wire 1 M# A1 $end
-$var wire 1 N# A2 $end
-$var wire 1 O# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 P# D $end
-$var wire 1 Q# Q $end
-$var reg 16 R# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[28] $end
-$scope module srl16e $end
-$var wire 1 S# A0 $end
-$var wire 1 T# A1 $end
-$var wire 1 U# A2 $end
-$var wire 1 V# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 W# D $end
-$var wire 1 X# Q $end
-$var reg 16 Y# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[29] $end
-$scope module srl16e $end
-$var wire 1 Z# A0 $end
-$var wire 1 [# A1 $end
-$var wire 1 \# A2 $end
-$var wire 1 ]# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 ^# D $end
-$var wire 1 _# Q $end
-$var reg 16 `# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[30] $end
-$scope module srl16e $end
-$var wire 1 a# A0 $end
-$var wire 1 b# A1 $end
-$var wire 1 c# A2 $end
-$var wire 1 d# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 e# D $end
-$var wire 1 f# Q $end
-$var reg 16 g# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[31] $end
-$scope module srl16e $end
-$var wire 1 h# A0 $end
-$var wire 1 i# A1 $end
-$var wire 1 j# A2 $end
-$var wire 1 k# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 l# D $end
-$var wire 1 m# Q $end
-$var reg 16 n# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[32] $end
-$scope module srl16e $end
-$var wire 1 o# A0 $end
-$var wire 1 p# A1 $end
-$var wire 1 q# A2 $end
-$var wire 1 r# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 s# D $end
-$var wire 1 t# Q $end
-$var reg 16 u# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[33] $end
-$scope module srl16e $end
-$var wire 1 v# A0 $end
-$var wire 1 w# A1 $end
-$var wire 1 x# A2 $end
-$var wire 1 y# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 z# D $end
-$var wire 1 {# Q $end
-$var reg 16 |# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[34] $end
-$scope module srl16e $end
-$var wire 1 }# A0 $end
-$var wire 1 ~# A1 $end
-$var wire 1 !$ A2 $end
-$var wire 1 "$ A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 #$ D $end
-$var wire 1 $$ Q $end
-$var reg 16 %$ data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[35] $end
-$scope module srl16e $end
-$var wire 1 &$ A0 $end
-$var wire 1 '$ A1 $end
-$var wire 1 ($ A2 $end
-$var wire 1 )$ A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 *$ D $end
-$var wire 1 +$ Q $end
-$var reg 16 ,$ data [15:0] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module fifo36_to_fifo19 $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 19 -$ f19_dataout [18:0] $end
-$var wire 1 ' f19_dst_rdy_i $end
-$var wire 1 ( f19_src_rdy_o $end
-$var wire 1 .$ f19_xfer $end
-$var wire 36 /$ f36_datain [35:0] $end
-$var wire 1 $ f36_dst_rdy_o $end
-$var wire 1 0$ f36_eof $end
-$var wire 1 1$ f36_occ $end
-$var wire 1 2$ f36_sof $end
-$var wire 1 % f36_src_rdy_i $end
-$var wire 1 3$ f36_xfer $end
-$var wire 1 4$ half_line $end
-$var wire 1 C reset $end
-$var reg 1 5$ phase $end
-$upscope $end
-$scope module fifo19_to_ll8 $end
-$var wire 1 6$ advance $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 19 7$ f19_data [18:0] $end
-$var wire 1 ' f19_dst_rdy_o $end
-$var wire 1 8$ f19_eof $end
-$var wire 1 9$ f19_occ $end
-$var wire 1 :$ f19_sof $end
-$var wire 1 ( f19_src_rdy_i $end
-$var wire 1 ;$ ll_dst_rdy $end
-$var wire 1 / ll_dst_rdy_n $end
-$var wire 1 <$ ll_eof $end
-$var wire 1 0 ll_eof_n $end
-$var wire 1 =$ ll_sof $end
-$var wire 1 1 ll_sof_n $end
-$var wire 1 >$ ll_src_rdy $end
-$var wire 1 2 ll_src_rdy_n $end
-$var wire 1 C reset $end
-$var reg 8 ?$ ll_data [7:0] $end
-$var reg 1 @$ state $end
-$upscope $end
-$scope module ll8_to_fifo19 $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 19 A$ f19_data [18:0] $end
-$var wire 1 * f19_dst_rdy_i $end
-$var wire 1 + f19_src_rdy_o $end
-$var wire 8 B$ ll_data [7:0] $end
-$var wire 1 C$ ll_dst_rdy $end
-$var wire 1 / ll_dst_rdy_n $end
-$var wire 1 D$ ll_eof $end
-$var wire 1 0 ll_eof_n $end
-$var wire 1 E$ ll_sof $end
-$var wire 1 1 ll_sof_n $end
-$var wire 1 F$ ll_src_rdy $end
-$var wire 1 2 ll_src_rdy_n $end
-$var wire 1 C reset $end
-$var wire 1 G$ xfer_out $end
-$var reg 8 H$ dat0 [7:0] $end
-$var reg 8 I$ dat1 [7:0] $end
-$var reg 1 J$ f19_eof $end
-$var reg 1 K$ f19_occ $end
-$var reg 1 L$ f19_sof $end
-$var reg 2 M$ state [1:0] $end
-$upscope $end
-$scope module fifo19_to_fifo36 $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
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diff --git a/fpga/usrp2/fifo/fifo_tb.v b/fpga/usrp2/fifo/fifo_tb.v
index f561df7fa..327da4700 100644
--- a/fpga/usrp2/fifo/fifo_tb.v
+++ b/fpga/usrp2/fifo/fifo_tb.v
@@ -24,20 +24,39 @@ module fifo_new_tb();
wire i1_sr, i1_dr;
wire i2_sr, i2_dr;
wire i3_sr, i3_dr;
+ wire i7_sr, i7_dr;
+
reg i4_dr = 0;
wire i4_sr;
- wire [35:0] i1, i4;
+ wire [35:0] i1, i4, i7;
wire [18:0] i2, i3;
wire [7:0] ll_data;
wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
+ wire [35:0] err_dat;
+ wire err_src_rdy, err_dst_rdy;
+
+ reg trigger = 0;
+ initial #10000 trigger = 1;
fifo_short #(.WIDTH(36)) fifo_short1
(.clk(clk),.reset(rst),.clear(clear),
.datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
- .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
+ .dataout(i7),.src_rdy_o(i7_sr),.dst_rdy_i(i7_dr) );
+ gen_context_pkt #(.PROT_ENG_FLAGS(1)) gcp
+ (.clk(clk),.reset(rst),.clear(clear),
+ .trigger(trigger), .sent(),
+ .streamid(32'hDEAD_F00D), .vita_time(64'h01234567_89ABCDEF), .message(32'hBEEF_2940),
+ .data_o(err_dat), .src_rdy_o(err_src_rdy), .dst_rdy_i(err_dst_rdy));
+
+ fifo36_mux #(.prio(0)) fifo36_mux
+ (.clk(clk), .reset(rst), .clear(clear),
+ .data0_i(i7), .src0_rdy_i(i7_sr), .dst0_rdy_o(i7_dr),
+ .data1_i(err_dat), .src1_rdy_i(err_src_rdy), .dst1_rdy_o(err_dst_rdy),
+ .data_o(i1), .src_rdy_o(i1_sr), .dst_rdy_i(i1_dr));
+
fifo36_to_fifo19 fifo36_to_fifo19
(.clk(clk),.reset(rst),.clear(clear),
.f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
@@ -59,7 +78,7 @@ module fifo_new_tb();
(.clk(clk),.reset(rst),.clear(clear),
.f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
.f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
-
+
task ReadFromFIFO36;
begin
$display("Read from FIFO36");
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v
index a7c686e7e..81587e25c 100644
--- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v
@@ -125,7 +125,7 @@ module aeMB_bpcu (/*AUTOARG*/
reg [31:2] rPC, xPC;
reg [31:2] rPCLNK, xPCLNK;
- assign iwb_adr_o = rIPC[IW-1:2];
+ assign iwb_adr_o = gena ? xIPC[IW-1:2] : rIPC[IW-1:2]; //IJB
always @(/*AUTOSENSE*/rBRA or rIPC or rPC or rRESULT) begin
//xPCLNK <= (^rATOM) ? rPC : rPC;
@@ -168,7 +168,8 @@ module aeMB_bpcu (/*AUTOARG*/
rATOM <= 2'h0;
rBRA <= 1'h0;
rDLY <= 1'h0;
- rIPC <= 30'h0;
+// rIPC <= 30'h0;
+ rIPC <= 30'h3fffffff; // DWORD aligned address
rPC <= 30'h0;
rPCLNK <= 30'h0;
// End of automatics
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
index 9ffa20ff2..38ca3a023 100644
--- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
@@ -10,12 +10,10 @@ module aeMB_core_BE
parameter MUL=0, parameter BSF=0)
(input sys_clk_i,
input sys_rst_i,
-
- output iwb_stb_o,
- output [ISIZ-1:0] iwb_adr_o,
- input [31:0] iwb_dat_i,
- input iwb_ack_i,
-
+ // Instruction port
+ output [14:0] if_adr,
+ input [31:0] if_dat,
+ // Data port
output dwb_we_o,
output dwb_stb_o,
output [DSIZ-1:0] dwb_adr_o,
@@ -28,17 +26,28 @@ module aeMB_core_BE
input sys_int_i,
input sys_exc_i);
- assign dwb_cyc_o = dwb_stb_o;
+ wire [ISIZ-1:0] iwb_adr_o;
+ wire [31:0] iwb_dat_i;
+ wire iwb_ack_i;
+ wire iwb_stb_o;
+
+ assign dwb_cyc_o = dwb_stb_o;
+ assign iwb_ack_i = 1'b1;
+ assign if_adr = iwb_adr_o[14:0];
+ assign iwb_dat_i = if_dat;
+
+ // Note some "wishbone" instruction fetch signals pruned on external interface
+ // but not propogated change deep into aeMB.
aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF))
aeMB_edk32 (.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i),
-
+ // Instruction Port
.iwb_stb_o(iwb_stb_o),
.iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
.iwb_ack_i(iwb_ack_i),
.iwb_dat_i(iwb_dat_i),
-
+ // Data port
.dwb_wre_o(dwb_we_o),
.dwb_stb_o(dwb_stb_o),
.dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
diff --git a/fpga/usrp2/sdr_lib/dsp_core_tx.v b/fpga/usrp2/sdr_lib/dsp_core_tx.v
index 22d3d44a3..79d92c9b3 100644
--- a/fpga/usrp2/sdr_lib/dsp_core_tx.v
+++ b/fpga/usrp2/sdr_lib/dsp_core_tx.v
@@ -29,11 +29,11 @@ module dsp_core_tx
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({scale_i,scale_q}),.changed());
- setting_reg #(.my_addr(BASE+2)) sr_2
+ setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed());
- setting_reg #(.my_addr(BASE+4)) sr_4
+ setting_reg #(.my_addr(BASE+4), .width(8)) sr_4
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({dacmux_b,dacmux_a}),.changed());
diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v
index b67d8edd6..9ba3cc136 100644..100755
--- a/fpga/usrp2/top/u2_rev3/u2_core.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core.v
@@ -277,33 +277,33 @@ module u2_core
// ///////////////////////////////////////////////////////////////////
// RAM Loader
- wire [31:0] ram_loader_dat, iwb_dat;
- wire [15:0] ram_loader_adr, iwb_adr;
+ wire [31:0] ram_loader_dat, if_dat;
+ wire [15:0] ram_loader_adr;
+ wire [14:0] if_adr;
wire [3:0] ram_loader_sel;
- wire ram_loader_stb, ram_loader_we, ram_loader_ack;
+ wire ram_loader_stb, ram_loader_we;
wire iwb_ack, iwb_stb;
ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
- ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+ ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst),
+ .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr),
+ .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel),
+ .wb_we(ram_loader_we),
+ .ram_loader_done(ram_loader_done),
// CPLD Interface
- .cfg_clk_i(cpld_clk),
- .cfg_data_i(cpld_din),
- .start_o(cpld_start_int),
- .mode_o(cpld_mode_int),
- .done_o(cpld_done_int),
- .detached_i(cpld_detached),
- // Wishbone Interface
- .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
- .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
- .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
- .ram_loader_done_o(ram_loader_done));
-
+ .cpld_clk(cpld_clk),
+ .cpld_din(cpld_din),
+ .cpld_start(cpld_start_int),
+ .cpld_mode(cpld_mode_int),
+ .cpld_done(cpld_done_int),
+ .cpld_detached(cpld_detached));
+
// /////////////////////////////////////////////////////////////////////////
// Processor
aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
// Instruction Wishbone bus to I-RAM
- .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
- .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+ .if_adr(if_adr),
+ .if_dat(if_dat),
// Data Wishbone bus to system bus fabric
.dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
.dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
@@ -317,16 +317,16 @@ module u2_core
// I-port connects directly to processor and ram loader
wire flush_icache;
- ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+ ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
.ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
.ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
- .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
+ .ram_loader_we_i(ram_loader_we),
.ram_loader_done_i(ram_loader_done),
- .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
- .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
+ .if_adr(if_adr),
+ .if_data(if_dat),
.dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
.dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
@@ -622,7 +622,7 @@ module u2_core
// ///////////////////////////////////////////////////////////////////////////////////
// External RAM Interface
-
+/*
localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes
wire [15:0] bus2ram, ram2bus;
@@ -650,6 +650,7 @@ module u2_core
.sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
.sram_mode(),.sram_zz() );
+*/
assign RAM_CE1n = 0;
assign RAM_D[17:16] = 2'bzz;
@@ -700,7 +701,8 @@ module u2_core
{ wr2_flags, rd2_flags },
{ GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
- assign debug_gpio_0 = debug_mac; //eth_mac_debug;
+ assign debug_gpio_0 = 0;
+ //debug_mac; //eth_mac_debug;
assign debug_gpio_1 = 0;
endmodule // u2_core
diff --git a/fpga/usrp2/top/u2_rev3/u2_core_udp.v b/fpga/usrp2/top/u2_rev3/u2_core_udp.v
index cb0ed78c7..b79cab5fb 100644
--- a/fpga/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core_udp.v
@@ -180,6 +180,11 @@ module u2_core
wire [31:0] irq;
wire [63:0] vita_time;
+ wire run_rx, run_tx;
+ reg run_rx_d1;
+ always @(posedge dsp_clk)
+ run_rx_d1 <= run_rx;
+
// ///////////////////////////////////////////////////////////////////////////////////////////////
// Wishbone Single Master INTERCON
localparam dw = 32; // Data bus width
@@ -279,33 +284,33 @@ module u2_core
// ///////////////////////////////////////////////////////////////////
// RAM Loader
- wire [31:0] ram_loader_dat, iwb_dat;
- wire [15:0] ram_loader_adr, iwb_adr;
+ wire [31:0] ram_loader_dat, if_dat;
+ wire [15:0] ram_loader_adr;
+ wire [14:0] if_adr;
wire [3:0] ram_loader_sel;
- wire ram_loader_stb, ram_loader_we, ram_loader_ack;
+ wire ram_loader_stb, ram_loader_we;
wire iwb_ack, iwb_stb;
ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
- ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+ ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst),
+ .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr),
+ .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel),
+ .wb_we(ram_loader_we),
+ .ram_loader_done(ram_loader_done),
// CPLD Interface
- .cfg_clk_i(cpld_clk),
- .cfg_data_i(cpld_din),
- .start_o(cpld_start_int),
- .mode_o(cpld_mode_int),
- .done_o(cpld_done_int),
- .detached_i(cpld_detached),
- // Wishbone Interface
- .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
- .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
- .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
- .ram_loader_done_o(ram_loader_done));
-
+ .cpld_clk(cpld_clk),
+ .cpld_din(cpld_din),
+ .cpld_start(cpld_start_int),
+ .cpld_mode(cpld_mode_int),
+ .cpld_done(cpld_done_int),
+ .cpld_detached(cpld_detached));
+
// /////////////////////////////////////////////////////////////////////////
// Processor
aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
// Instruction Wishbone bus to I-RAM
- .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
- .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+ .if_adr(if_adr),
+ .if_dat(if_dat),
// Data Wishbone bus to system bus fabric
.dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
.dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
@@ -319,16 +324,16 @@ module u2_core
// I-port connects directly to processor and ram loader
wire flush_icache;
- ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+ ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
.ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
.ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
- .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
+ .ram_loader_we_i(ram_loader_we),
.ram_loader_done_i(ram_loader_done),
- .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
- .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
+ .if_adr(if_adr),
+ .if_data(if_dat),
.dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
.dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
@@ -461,11 +466,20 @@ module u2_core
.tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy),
.debug(debug_udp) );
+ wire [35:0] tx_err_data, udp1_tx_data;
+ wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy;
+
fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
- .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
+ .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy));
+ fifo36_mux #(.prio(0)) mux_err_stream
+ (.clk(dsp_clk), .reset(dsp_reset), .clear(0),
+ .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy),
+ .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
+ .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
+
fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy),
@@ -509,12 +523,13 @@ module u2_core
// In Rev3 there are only 6 leds, and the highest one is on the ETH connector
wire [7:0] led_src, led_sw;
- wire [7:0] led_hw = {clk_status,serdes_link_up};
+ wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0};
setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(led_sw),.changed());
- setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(led_src),.changed());
+
+ setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110))
+ sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed());
assign leds = (led_src & led_hw) | (~led_src & led_sw);
@@ -565,11 +580,6 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// ATR Controller, Slave #11
- wire run_rx, run_tx;
- reg run_rx_d1;
- always @(posedge dsp_clk)
- run_rx_d1 <= run_rx;
-
atr_controller atr_controller
(.clk_i(wb_clk),.rst_i(wb_rst),
.adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
@@ -638,40 +648,26 @@ module u2_core
// DSP TX
wire [35:0] tx_data;
- wire [99:0] tx1_data;
- wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy;
-
- wire [31:0] debug_vtc, debug_vtd, debug_vt;
+ wire tx_src_rdy, tx_dst_rdy;
+ wire [31:0] debug_vt;
fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i),
.dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
- vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
- .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
- .debug(debug_vtd) );
-
- vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .vita_time(vita_time),.underrun(underrun),
- .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
- .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
- .debug(debug_vtc) );
-
- assign debug_vt = debug_vtc | debug_vtd;
-
- dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx
- (.clk(dsp_clk),.rst(dsp_rst),
+ vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
+ .REPORT_ERROR(1), .PROT_ENG_FLAGS(1))
+ vita_tx_chain
+ (.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .vita_time(vita_time),
+ .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
+ .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
.dac_a(dac_a),.dac_b(dac_b),
- .debug(debug_tx_dsp) );
-
+ .underrun(underrun), .run(run_tx),
+ .debug(debug_vt));
+
assign dsp_rst = wb_rst;
// ///////////////////////////////////////////////////////////////////////////////////
@@ -773,8 +769,7 @@ endmodule // u2_core
{ s6_adr[15:8] },
{ s6_adr[7:0] },
{ 6'd0, mdio_cpy, MDC } };
-*/
-/*
+
assign debug = { { GMII_TXD },
{ 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK },
{ wr2_flags, rd2_flags },
@@ -783,7 +778,6 @@ endmodule // u2_core
{ 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK },
{ wr2_flags, rd2_flags },
{ GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
- */
// assign debug = debug_udp;
// assign debug = vrc_debug;
@@ -794,9 +788,8 @@ endmodule // u2_core
{wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}};
*/
// assign debug_gpio_1 = {vita_time[63:32] };
-
-/*
- assign debug_gpio_1 = { { tx_f19_data[15:8] },
+/*
+ assign debug_gpio_1 = { { tx_f19_data[15:8] },
{ tx_f19_data[7:0] },
{ 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] },
{ 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } };
diff --git a/fpga/usrp2/udp/prot_eng_tx.v b/fpga/usrp2/udp/prot_eng_tx.v
index 9031011f7..a18eb73ae 100644
--- a/fpga/usrp2/udp/prot_eng_tx.v
+++ b/fpga/usrp2/udp/prot_eng_tx.v
@@ -40,11 +40,16 @@ module prot_eng_tx
// Store header values in a small dual-port (distributed) ram
reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1];
wire [HDR_WIDTH-1:0] header_word;
+ reg [15:0] chk_precompute;
always @(posedge clk)
if(set_stb & ((set_addr & 8'hE0) == BASE))
- header_ram[set_addr[4:0]] <= set_data;
-
+ begin
+ header_ram[set_addr[4:0]] <= set_data;
+ if(set_data[18])
+ chk_precompute <= set_data[15:0];
+ end
+
assign header_word = header_ram[state];
wire last_hdr_line = header_word[19];
@@ -56,7 +61,7 @@ module prot_eng_tx
reg [15:0] length;
wire [15:0] ip_length = length + 28; // IP HDR + UDP HDR
wire [15:0] udp_length = length + 8; // UDP HDR
-
+
always @(posedge clk)
if(reset)
begin
@@ -101,12 +106,16 @@ module prot_eng_tx
wire [15:0] checksum;
add_onescomp #(.WIDTH(16)) add_onescomp
- (.A(header_word[15:0]),.B(ip_length),.SUM(checksum));
+ (.A(chk_precompute),.B(ip_length),.SUM(checksum));
+ reg [15:0] checksum_reg;
+ always @(posedge clk)
+ checksum_reg <= checksum;
+
always @*
if(ip_chk)
//dataout_int <= header_word[15:0] ^ ip_length;
- dataout_int <= 16'hFFFF ^ checksum;
+ dataout_int <= 16'hFFFF ^ checksum_reg;
else if(ip_len)
dataout_int <= ip_length;
else if(udp_len)
diff --git a/fpga/usrp2/vrt/Makefile.srcs b/fpga/usrp2/vrt/Makefile.srcs
index 07c62224b..dc4bd8c96 100644
--- a/fpga/usrp2/vrt/Makefile.srcs
+++ b/fpga/usrp2/vrt/Makefile.srcs
@@ -10,4 +10,6 @@ vita_rx_control.v \
vita_rx_framer.v \
vita_tx_control.v \
vita_tx_deframer.v \
+vita_tx_chain.v \
+gen_context_pkt.v \
))
diff --git a/fpga/usrp2/vrt/gen_context_pkt.v b/fpga/usrp2/vrt/gen_context_pkt.v
new file mode 100644
index 000000000..780a027ba
--- /dev/null
+++ b/fpga/usrp2/vrt/gen_context_pkt.v
@@ -0,0 +1,72 @@
+
+
+module gen_context_pkt
+ #(parameter PROT_ENG_FLAGS=1)
+ (input clk, input reset, input clear,
+ input trigger, output sent,
+ input [31:0] streamid,
+ input [63:0] vita_time,
+ input [31:0] message,
+ output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+ localparam CTXT_IDLE = 0;
+ localparam CTXT_PROT_ENG = 1;
+ localparam CTXT_HEADER = 2;
+ localparam CTXT_STREAMID = 3;
+ localparam CTXT_SECS = 4;
+ localparam CTXT_TICS = 5;
+ localparam CTXT_TICS2 = 6;
+ localparam CTXT_MESSAGE = 7;
+ localparam CTXT_DONE = 8;
+
+ reg [33:0] data_int;
+ wire src_rdy_int, dst_rdy_int;
+ wire [3:0] seqno = 0;
+ reg [3:0] ctxt_state;
+ reg [63:0] err_time;
+
+ always @(posedge clk)
+ if(reset | clear)
+ ctxt_state <= CTXT_IDLE;
+ else
+ case(ctxt_state)
+ CTXT_IDLE :
+ if(trigger)
+ begin
+ err_time <= vita_time;
+ if(PROT_ENG_FLAGS)
+ ctxt_state <= CTXT_PROT_ENG;
+ else
+ ctxt_state <= CTXT_HEADER;
+ end
+
+ CTXT_DONE :
+ if(~trigger)
+ ctxt_state <= CTXT_IDLE;
+
+ default :
+ if(dst_rdy_int)
+ ctxt_state <= ctxt_state + 1;
+ endcase // case (ctxt_state)
+
+ assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) );
+
+ always @*
+ case(ctxt_state)
+ CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd24 };
+ CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd6 };
+ CTXT_STREAMID : data_int <= { 2'b00, streamid };
+ CTXT_SECS : data_int <= { 2'b00, err_time[63:32] };
+ CTXT_TICS : data_int <= { 2'b00, 32'd0 };
+ CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] };
+ CTXT_MESSAGE : data_int <= { 2'b10, message };
+ default : data_int <= {2'b00, 32'b00};
+ endcase // case (ctxt_state)
+
+ fifo_short #(.WIDTH(34)) ctxt_fifo
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
+ .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
+ assign data_o[35:34] = 2'b00;
+
+endmodule // gen_context_pkt
diff --git a/fpga/usrp2/vrt/vita_rx.build b/fpga/usrp2/vrt/vita_rx.build
index f6d2d75a3..010d1be6e 100755
--- a/fpga/usrp2/vrt/vita_rx.build
+++ b/fpga/usrp2/vrt/vita_rx.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v
+iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v
diff --git a/fpga/usrp2/vrt/vita_rx_control.v b/fpga/usrp2/vrt/vita_rx_control.v
index 742dd47e0..93673d292 100644
--- a/fpga/usrp2/vrt/vita_rx_control.v
+++ b/fpga/usrp2/vrt/vita_rx_control.v
@@ -67,7 +67,7 @@ module vita_rx_control
shortfifo #(.WIDTH(96)) commandfifo
(.clk(clk),.rst(reset),.clear(clear_int),
.datain({new_command,new_time}), .write(write_ctrl&~full_ctrl), .full(full_ctrl),
- .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}),
+ .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}),
.read(read_ctrl), .empty(empty_ctrl),
.occupied(command_queue_len), .space() );
@@ -98,7 +98,7 @@ module vita_rx_control
.src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i),
.space(), .occupied() );
- // Inband Signallling State Machine
+ // Inband Signalling State Machine
time_compare
time_compare (.time_now(vita_time), .trigger_time(rcvtime), .now(now), .early(early), .late(late));
@@ -189,4 +189,3 @@ module vita_rx_control
{ 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} };
endmodule // rx_control
-
diff --git a/fpga/usrp2/vrt/vita_rx_framer.v b/fpga/usrp2/vrt/vita_rx_framer.v
index f3a81664a..fd82263d0 100644
--- a/fpga/usrp2/vrt/vita_rx_framer.v
+++ b/fpga/usrp2/vrt/vita_rx_framer.v
@@ -99,7 +99,7 @@ module vita_rx_framer
localparam VITA_ERR_TICS = 12;
localparam VITA_ERR_TICS2 = 13;
localparam VITA_ERR_PAYLOAD = 14;
- localparam VITA_ERR_TRAILER = 15;
+ localparam VITA_ERR_TRAILER = 15; // Extension context packets have no trailer
always @(posedge clk)
if(reset | clear_pkt_count)
@@ -107,17 +107,30 @@ module vita_rx_framer
else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy)
pkt_count <= pkt_count + 1;
+ wire has_streamid = vita_header[28];
+ wire has_trailer = vita_header[26];
+ reg trl_eob;
+
always @*
case(vita_state)
- VITA_HEADER, VITA_ERR_HEADER : pkt_fifo_line <= {2'b01,vita_header[31:20],pkt_count,vita_pkt_len};
- VITA_STREAMID, VITA_ERR_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
- VITA_SECS, VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
- VITA_TICS, VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
- VITA_TICS2, VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
+ // Data packets are IF Data packets with or w/o streamid, no classid, with trailer
+ VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:20],pkt_count,vita_pkt_len};
+ VITA_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
+ VITA_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
+ VITA_TICS : pkt_fifo_line <= {2'b00,32'd0};
+ VITA_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
VITA_PAYLOAD : pkt_fifo_line <= {2'b00,data_fifo_o};
- VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b00,28'd0,flags_fifo_o};
- VITA_TRAILER : pkt_fifo_line <= {2'b10,vita_trailer};
- VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
+ VITA_TRAILER : pkt_fifo_line <= {2'b10,vita_trailer[31:21],1'b1,vita_trailer[19:9],trl_eob,8'd0};
+
+ // Error packets are Extension Context packets, which have no trailer
+ VITA_ERR_HEADER : pkt_fifo_line <= {2'b01,4'b0101,4'b0000,vita_header[23:20],pkt_count,16'd6};
+ VITA_ERR_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
+ VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
+ VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
+ VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
+ VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b11,28'd0,flags_fifo_o};
+ //VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
+
default : pkt_fifo_line <= 34'h0_FFFF_FFFF;
endcase // case (vita_state)
@@ -141,6 +154,11 @@ module vita_rx_framer
end
else if(pkt_fifo_rdy)
case(vita_state)
+ VITA_HEADER :
+ if(has_streamid)
+ vita_state <= VITA_STREAMID;
+ else
+ vita_state <= VITA_SECS;
VITA_PAYLOAD :
if(sample_fifo_src_rdy_i)
begin
@@ -148,6 +166,7 @@ module vita_rx_framer
begin
sample_phase <= 0;
sample_ctr <= sample_ctr + 1;
+ trl_eob <= flags_fifo_o[0];
if(sample_ctr == samples_per_packet)
vita_state <= VITA_TRAILER;
if(|flags_fifo_o) // end early if any flag is set
@@ -155,8 +174,10 @@ module vita_rx_framer
end
else
sample_phase <= sample_phase + 1;
- end
- VITA_TRAILER, VITA_ERR_TRAILER :
+ end // if (sample_fifo_src_rdy_i)
+ VITA_ERR_PAYLOAD :
+ vita_state <= VITA_IDLE;
+ VITA_TRAILER :
vita_state <= VITA_IDLE;
default :
vita_state <= vita_state + 1;
@@ -172,7 +193,7 @@ module vita_rx_framer
VITA_PAYLOAD :
// Write if sample ready and no error flags
req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]);
- VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD, VITA_ERR_TRAILER :
+ VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD :
req_write_pkt_fifo <= 1;
default :
req_write_pkt_fifo <= 0;
@@ -192,7 +213,7 @@ module vita_rx_framer
( ((vita_state==VITA_PAYLOAD) &
(sample_phase == (numchan-4'd1)) &
~|flags_fifo_o[3:1]) |
- (vita_state==VITA_ERR_TRAILER));
+ (vita_state==VITA_ERR_PAYLOAD));
assign debug_rx = vita_state;
diff --git a/fpga/usrp2/vrt/vita_rx_tb.v b/fpga/usrp2/vrt/vita_rx_tb.v
index b4fda9622..3e01e2ee2 100644
--- a/fpga/usrp2/vrt/vita_rx_tb.v
+++ b/fpga/usrp2/vrt/vita_rx_tb.v
@@ -3,8 +3,8 @@
module vita_rx_tb;
localparam DECIM = 8'd4;
- localparam MAXCHAN=4;
- localparam NUMCHAN=4;
+ localparam MAXCHAN=1;
+ localparam NUMCHAN=1;
reg clk = 0;
reg reset = 1;
@@ -94,7 +94,7 @@ module vita_rx_tb;
@(posedge clk);
write_setting(4,32'hDEADBEEF); // VITA header
write_setting(5,32'hF00D1234); // VITA streamid
- write_setting(6,32'h98765432); // VITA trailer
+ write_setting(6,32'hF0000000); // VITA trailer
write_setting(7,8); // Samples per VITA packet
write_setting(8,NUMCHAN); // Samples per VITA packet
queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet
@@ -111,8 +111,13 @@ module vita_rx_tb;
queue_rx_cmd(0,0,8,32'h0,32'h340); // send at, on time
queue_rx_cmd(0,0,8,32'h0,32'h100); // send at, but late
+ #100000;
+ $display("\nChained, break chain\n");
queue_rx_cmd(1,1,8,32'h0,32'h0); // chained, but break chain
#100000;
+ $display("\nSingle packet\n");
+ queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet
+ #100000;
$display("\nEnd chain with zero samples, shouldn't error\n");
queue_rx_cmd(1,1,8,32'h0,32'h0); // chained
queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error
diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v
new file mode 100644
index 000000000..662cdca62
--- /dev/null
+++ b/fpga/usrp2/vrt/vita_tx_chain.v
@@ -0,0 +1,71 @@
+
+module vita_tx_chain
+ #(parameter BASE_CTRL=0,
+ parameter BASE_DSP=0,
+ parameter REPORT_ERROR=0,
+ parameter PROT_ENG_FLAGS=0)
+ (input clk, input reset,
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+ input [63:0] vita_time,
+ input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o,
+ output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i,
+ output [15:0] dac_a, output [15:0] dac_b,
+ output underrun, output run,
+ output [31:0] debug);
+
+ localparam MAXCHAN = 1;
+ localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN);
+
+ wire [FIFOWIDTH-1:0] tx1_data;
+ wire tx1_src_rdy, tx1_dst_rdy;
+ wire clear_vita;
+ wire [31:0] sample_tx;
+ wire [31:0] streamid, message;
+ wire trigger, sent;
+ wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp;
+
+ wire error;
+ wire [31:0] error_code;
+ wire clear_seqnum;
+
+ assign underrun = error;
+ assign message = error_code;
+
+ setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(streamid),.changed(clear_seqnum));
+
+ vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(MAXCHAN)) vita_tx_deframer
+ (.clk(clk), .reset(reset), .clear(clear_vita), .clear_seqnum(clear_seqnum),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o),
+ .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
+ .debug(debug_vtd) );
+
+ vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control
+ (.clk(clk), .reset(reset), .clear(clear_vita),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .vita_time(vita_time),.error(error),.error_code(error_code),
+ .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
+ .sample(sample_tx), .run(run), .strobe(strobe_tx),
+ .debug(debug_vtc) );
+
+ dsp_core_tx #(.BASE(BASE_DSP)) dsp_core_tx
+ (.clk(clk),.rst(reset),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .sample(sample_tx), .run(run), .strobe(strobe_tx),
+ .dac_a(dac_a),.dac_b(dac_b),
+ .debug(debug_tx_dsp) );
+
+ generate
+ if(REPORT_ERROR==1)
+ gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt
+ (.clk(clk), .reset(reset), .clear(clear_vita),
+ .trigger(error), .sent(),
+ .streamid(streamid), .vita_time(vita_time), .message(message),
+ .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i));
+ endgenerate
+
+ assign debug = debug_vtc | debug_vtd;
+
+endmodule // vita_tx_chain
diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v
index bffc64e52..d0516bec8 100644
--- a/fpga/usrp2/vrt/vita_tx_control.v
+++ b/fpga/usrp2/vrt/vita_tx_control.v
@@ -6,10 +6,11 @@ module vita_tx_control
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [63:0] vita_time,
- output underrun,
+ output error,
+ output reg [31:0] error_code,
// From vita_tx_deframer
- input [4+64+WIDTH-1:0] sample_fifo_i,
+ input [5+64+16+WIDTH-1:0] sample_fifo_i,
input sample_fifo_src_rdy_i,
output sample_fifo_dst_rdy_o,
@@ -20,14 +21,17 @@ module vita_tx_control
output [31:0] debug
);
-
- assign sample = sample_fifo_i[4+64+WIDTH-1:4+64];
+
+ assign sample = sample_fifo_i[5+64+16+WIDTH-1:5+64+16];
wire [63:0] send_time = sample_fifo_i[63:0];
- wire eop = sample_fifo_i[64];
- wire eob = sample_fifo_i[65];
- wire sob = sample_fifo_i[66];
- wire send_at = sample_fifo_i[67];
+ wire [15:0] seqnum = sample_fifo_i[79:64];
+ wire eop = sample_fifo_i[80];
+ wire eob = sample_fifo_i[81];
+ wire sob = sample_fifo_i[82];
+ wire send_at = sample_fifo_i[83];
+ wire seqnum_err = sample_fifo_i[84];
+
wire now, early, late, too_early;
// FIXME ignore too_early for now for timing reasons
@@ -40,8 +44,15 @@ module vita_tx_control
localparam IBS_IDLE = 0;
localparam IBS_RUN = 1; // FIXME do we need this?
localparam IBS_CONT_BURST = 2;
- localparam IBS_UNDERRUN = 3;
- localparam IBS_UNDERRUN_DONE = 4;
+ localparam IBS_ERROR = 3;
+ localparam IBS_ERROR_DONE = 4;
+ localparam IBS_ERROR_WAIT = 5;
+
+ wire [31:0] CODE_UNDERRUN = {seqnum,16'd2};
+ wire [31:0] CODE_SEQ_ERROR = {seqnum,16'd4};
+ wire [31:0] CODE_TIME_ERROR = {seqnum,16'd8};
+ wire [31:0] CODE_UNDERRUN_MIDPKT = {seqnum,16'd16};
+ wire [31:0] CODE_SEQ_ERROR_MIDBURST = {seqnum,16'd32};
reg [2:0] ibs_state;
@@ -50,22 +61,49 @@ module vita_tx_control
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(clear_state));
+ wire [31:0] error_policy;
+ setting_reg #(.my_addr(BASE+3)) sr_error_policy
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(error_policy),.changed());
+
+ wire policy_wait = error_policy[0];
+ wire policy_next_packet = error_policy[1];
+ wire policy_next_burst = error_policy[2];
+ reg send_error;
+
always @(posedge clk)
if(reset | clear_state)
- ibs_state <= 0;
+ begin
+ ibs_state <= IBS_IDLE;
+ send_error <= 0;
+ end
else
case(ibs_state)
IBS_IDLE :
if(sample_fifo_src_rdy_i)
- if(~send_at | now)
+ if(seqnum_err)
+ begin
+ ibs_state <= IBS_ERROR;
+ error_code <= CODE_SEQ_ERROR;
+ send_error <= 1;
+ end
+ else if(~send_at | now)
ibs_state <= IBS_RUN;
else if(late | too_early)
- ibs_state <= IBS_UNDERRUN;
+ begin
+ ibs_state <= IBS_ERROR;
+ error_code <= CODE_TIME_ERROR;
+ send_error <= 1;
+ end
IBS_RUN :
if(strobe)
if(~sample_fifo_src_rdy_i)
- ibs_state <= IBS_UNDERRUN;
+ begin
+ ibs_state <= IBS_ERROR;
+ error_code <= CODE_UNDERRUN_MIDPKT;
+ send_error <= 1;
+ end
else if(eop)
if(eob)
ibs_state <= IBS_IDLE;
@@ -74,24 +112,53 @@ module vita_tx_control
IBS_CONT_BURST :
if(strobe)
- ibs_state <= IBS_UNDERRUN_DONE;
+ begin
+ if(policy_next_packet)
+ ibs_state <= IBS_ERROR_DONE;
+ else if(policy_wait)
+ ibs_state <= IBS_ERROR_WAIT;
+ else
+ ibs_state <= IBS_ERROR;
+ error_code <= CODE_UNDERRUN;
+ send_error <= 1;
+ end
else if(sample_fifo_src_rdy_i)
- ibs_state <= IBS_RUN;
+ if(seqnum_err)
+ begin
+ ibs_state <= IBS_ERROR;
+ error_code <= CODE_SEQ_ERROR_MIDBURST;
+ send_error <= 1;
+ end
+ else
+ ibs_state <= IBS_RUN;
- IBS_UNDERRUN :
- if(sample_fifo_src_rdy_i & eop)
- ibs_state <= IBS_UNDERRUN_DONE;
+ IBS_ERROR :
+ begin
+ send_error <= 0;
+ if(sample_fifo_src_rdy_i & eop)
+ if(policy_next_packet | (policy_next_burst & eob))
+ ibs_state <= IBS_IDLE;
+ else if(policy_wait)
+ ibs_state <= IBS_ERROR_WAIT;
+ end
- IBS_UNDERRUN_DONE :
- ;
+ IBS_ERROR_DONE :
+ begin
+ send_error <= 0;
+ ibs_state <= IBS_IDLE;
+ end
+
+ IBS_ERROR_WAIT :
+ send_error <= 0;
endcase // case (ibs_state)
- assign sample_fifo_dst_rdy_o = (ibs_state == IBS_UNDERRUN) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout
+ assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout
assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST);
- assign underrun = (ibs_state == IBS_UNDERRUN_DONE);
+ //assign error = (ibs_state == IBS_ERROR_DONE);
+ assign error = send_error;
assign debug = { { now,early,late,too_early,eop,eob,sob,send_at },
- { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, underrun, ibs_state[2:0] },
+ { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] },
{ 8'b0 },
{ 8'b0 } };
diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v
index 220d3b061..f9cd7d00d 100644
--- a/fpga/usrp2/vrt/vita_tx_deframer.v
+++ b/fpga/usrp2/vrt/vita_tx_deframer.v
@@ -2,7 +2,7 @@
module vita_tx_deframer
#(parameter BASE=0,
parameter MAXCHAN=1)
- (input clk, input reset, input clear,
+ (input clk, input reset, input clear, input clear_seqnum,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
// To FIFO interface of Buffer Pool
@@ -10,7 +10,7 @@ module vita_tx_deframer
input src_rdy_i,
output dst_rdy_o,
- output [4+64+(32*MAXCHAN)-1:0] sample_fifo_o,
+ output [5+64+16+(32*MAXCHAN)-1:0] sample_fifo_o,
output sample_fifo_src_rdy_o,
input sample_fifo_dst_rdy_i,
@@ -21,8 +21,10 @@ module vita_tx_deframer
output [31:0] debug
);
+ localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN);
+
wire [1:0] numchan;
- setting_reg #(.my_addr(BASE), .at_reset(0)) sr_numchan
+ setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(numchan),.changed());
@@ -36,14 +38,18 @@ module vita_tx_deframer
assign is_sob = data_i[25];
assign is_eob = data_i[24];
wire eof = data_i[33];
-
reg has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg;
reg has_trailer_reg, is_sob_reg, is_eob_reg;
-
+
reg [15:0] pkt_len;
reg [1:0] vector_phase;
wire line_done;
+ reg seqnum_err;
+ reg [3:0] seqnum_reg;
+ wire [3:0] seqnum = data_i[19:16];
+ wire [3:0] next_seqnum = seqnum_reg + 4'd1;
+
// Output FIFO for packetized data
localparam VITA_HEADER = 0;
localparam VITA_STREAMID = 1;
@@ -61,6 +67,13 @@ module vita_tx_deframer
wire eop = eof | (pkt_len==hdr_len); // FIXME would ignoring eof allow larger VITA packets?
wire fifo_space;
+
+ always @(posedge clk)
+ if(reset | clear_seqnum)
+ seqnum_reg <= 4'hF;
+ else
+ if((vita_state==VITA_HEADER) & src_rdy_i)
+ seqnum_reg <= seqnum;
always @(posedge clk)
if(reset | clear)
@@ -68,6 +81,7 @@ module vita_tx_deframer
vita_state <= VITA_HEADER;
{has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg}
<= 0;
+ seqnum_err <= 0;
end
else
if((vita_state == VITA_STORE) & fifo_space)
@@ -99,6 +113,7 @@ module vita_tx_deframer
vita_state <= VITA_TICS;
else
vita_state <= VITA_PAYLOAD;
+ seqnum_err <= ~(seqnum == next_seqnum);
end // case: VITA_HEADER
VITA_STREAMID :
if(has_classid_reg)
@@ -145,7 +160,7 @@ module vita_tx_deframer
assign line_done = (vector_phase == numchan);
- wire [4+64+32*MAXCHAN-1:0] fifo_i;
+ wire [FIFOWIDTH-1:0] fifo_i;
reg [63:0] send_time;
reg [31:0] sample_a, sample_b, sample_c, sample_d;
@@ -169,13 +184,14 @@ module vita_tx_deframer
endcase // case (vector_phase)
wire store = (vita_state == VITA_STORE);
- fifo_short #(.WIDTH(4+64+32*MAXCHAN)) short_tx_q
+ fifo_short #(.WIDTH(FIFOWIDTH)) short_tx_q
(.clk(clk), .reset(reset), .clear(clear),
.datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space),
.dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i) );
// sob, eob, has_secs (send_at) ignored on all lines except first
- assign fifo_i = {sample_d,sample_c,sample_b,sample_a,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time};
+ assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop,
+ 12'd0,seqnum_reg,send_time};
assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 08:48:11 +0000