reduce warnings, modernize testbench

6 files changed, 25 insertions, 28 deletions

diff --git a/usrp2/simple_gemac/eth_tasks_f36.v b/usrp2/simple_gemac/eth_tasks_f36.v
index efd72778b..dc64971d4 100644
--- a/usrp2/simple_gemac/eth_tasks_f36.v
+++ b/usrp2/simple_gemac/eth_tasks_f36.v
@@ -4,11 +4,11 @@ task SendFlowCtrl;
    input [15:0] fc_len;
    begin
       $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
-      pause_time <= fc_len;
+      //pause_time <= fc_len;
       @(posedge eth_clk);
-      pause_req <= 1;
+      //pause_req <= 1;
       @(posedge eth_clk);
-      pause_req <= 0;
+      //pause_req <= 0;
       $display("Sent Flow Control");
    end
 endtask // SendFlowCtrl
diff --git a/usrp2/simple_gemac/simple_gemac_wb.v b/usrp2/simple_gemac/simple_gemac_wb.v
index f4ecd7f08..1ef38be11 100644
--- a/usrp2/simple_gemac/simple_gemac_wb.v
+++ b/usrp2/simple_gemac/simple_gemac_wb.v
@@ -1,16 +1,17 @@
 
 module wb_reg
   #(parameter ADDR=0,
-    parameter DEFAULT=0)
+    parameter DEFAULT=0,
+    parameter WIDTH=32)
    (input clk, input rst, 
     input [5:0] adr, input wr_acc,
-    input [31:0] dat_i, output reg [31:0] dat_o);
+    input [31:0] dat_i, output reg [WIDTH-1:0] dat_o);
 
    always @(posedge clk)
      if(rst)
        dat_o <= DEFAULT;
      else if(wr_acc & (adr == ADDR))
-       dat_o <= dat_i;
+       dat_o <= dat_i[WIDTH-1:0];
    
 endmodule // wb_reg
 
@@ -41,19 +42,19 @@ module simple_gemac_wb
    wire [6:0] misc_settings;
    assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings;
 
-   wb_reg #(.ADDR(0),.DEFAULT(7'b0111011))
+   wb_reg #(.ADDR(0),.DEFAULT(7'b0111011),.WIDTH(7))
    wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		    .dat_i(wb_dat_i), .dat_o(misc_settings) );
-   wb_reg #(.ADDR(1),.DEFAULT(0))
+   wb_reg #(.ADDR(1),.DEFAULT(0),.WIDTH(16))
    wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		   .dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) );
-   wb_reg #(.ADDR(2),.DEFAULT(0))
+   wb_reg #(.ADDR(2),.DEFAULT(0),.WIDTH(32))
    wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		   .dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) );
-   wb_reg #(.ADDR(3),.DEFAULT(0))
+   wb_reg #(.ADDR(3),.DEFAULT(0),.WIDTH(16))
    wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		   .dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) );
-   wb_reg #(.ADDR(4),.DEFAULT(0))
+   wb_reg #(.ADDR(4),.DEFAULT(0),.WIDTH(32))
    wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		   .dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) );
 
@@ -80,15 +81,15 @@ module simple_gemac_wb
    reg [15:0]  MIIRX_DATA;
    wire [2:0]  MIISTATUS;
 
-   wb_reg #(.ADDR(5),.DEFAULT(0))
+   wb_reg #(.ADDR(5),.DEFAULT(0),.WIDTH(9))
    wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		    .dat_i(wb_dat_i), .dat_o({NoPre,Divider}) );
    
-   wb_reg #(.ADDR(6),.DEFAULT(0))
+   wb_reg #(.ADDR(6),.DEFAULT(0),.WIDTH(13))
    wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		   .dat_i(wb_dat_i), .dat_o(MIIADDRESS) );
    
-   wb_reg #(.ADDR(7),.DEFAULT(0))
+   wb_reg #(.ADDR(7),.DEFAULT(0),.WIDTH(16))
    wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		   .dat_i(wb_dat_i), .dat_o(CtrlData) );
    
@@ -133,11 +134,11 @@ module simple_gemac_wb
       .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), 
       .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) );
 
-   wb_reg #(.ADDR(11),.DEFAULT(0))
+   wb_reg #(.ADDR(11),.DEFAULT(0),.WIDTH(16))
    wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		     .dat_i(wb_dat_i), .dat_o(pause_time) );
    
-   wb_reg #(.ADDR(12),.DEFAULT(0))
+   wb_reg #(.ADDR(12),.DEFAULT(0),.WIDTH(16))
    wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		       .dat_i(wb_dat_i), .dat_o(pause_thresh) );
    
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.build b/usrp2/simple_gemac/simple_gemac_wrapper.build
index 30f65ab17..9293deca6 100755
--- a/usrp2/simple_gemac/simple_gemac_wrapper.build
+++ b/usrp2/simple_gemac/simple_gemac_wrapper.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
+iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19.build b/usrp2/simple_gemac/simple_gemac_wrapper19.build
index 4be0aac1f..b9475baa2 100755
--- a/usrp2/simple_gemac/simple_gemac_wrapper19.build
+++ b/usrp2/simple_gemac/simple_gemac_wrapper19.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v
+iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
index 7d57542dc..b61d60d30 100644
--- a/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
+++ b/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
@@ -44,12 +44,12 @@ module simple_gemac_wrapper19_tb;
    reg 	       wb_stb=0, wb_cyc=0, wb_we=0;
    wire        wb_ack;
 
-   reg [18:0]  tx_f19_data=0;
+   reg [19:0]  tx_f19_data=0;
    reg 	       tx_f19_src_rdy = 0;
    wire        tx_f19_dst_rdy;
-   wire [35:0] rx_f36_data;
-   wire        rx_f36_src_rdy;
-   wire        rx_f36_dst_rdy = 1;
+   wire [35:0] rx_f19_data;
+   wire        rx_f19_src_rdy;
+   wire        rx_f19_dst_rdy = 1;
    
    simple_gemac_wrapper19 simple_gemac_wrapper19
      (.clk125(eth_clk),  .reset(reset),
@@ -59,7 +59,7 @@ module simple_gemac_wrapper19_tb;
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
       //.pause_req(pause_req), .pause_time(pause_time),
 
-      .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
+      .sys_clk(sys_clk), .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
       .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
 
       .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
index 26a471a49..0aadc7e93 100644
--- a/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
+++ b/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
@@ -24,9 +24,6 @@ module simple_gemac_wrapper_tb;
    
    wire [7:0] rx_data, tx_data;
    
-   reg [15:0] pause_time;
-   reg pause_req      = 0;
-
    wire GMII_RX_CLK   = GMII_GTX_CLK;
 
    reg [7:0] FORCE_DAT_ERR = 0;
@@ -47,7 +44,7 @@ module simple_gemac_wrapper_tb;
    reg [35:0]  tx_f36_data=0;
    reg 	       tx_f36_src_rdy = 0;
    wire        tx_f36_dst_rdy;
-   wire        rx_f36_data;
+   wire [35:0] rx_f36_data;
    wire        rx_f36_src_rdy;
    wire        rx_f36_dst_rdy = 1;
    
@@ -57,7 +54,6 @@ module simple_gemac_wrapper_tb;
       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
-      .pause_req(pause_req), .pause_time(pause_time),
 
       .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
       .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),