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authorMatt Ettus <matt@ettus.com>2011-03-28 15:09:30 -0700
committerMatt Ettus <matt@ettus.com>2011-05-26 17:31:22 -0700
commitd0bfde4213dcab7fe3c5db404ef0f01354d56f67 (patch)
tree0159284dd5f97912177321d57627765a906e1b52
parentdcabd7f30c60283533d28376fcf5cd38725fd437 (diff)
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u1p: do padding outside of gpif_rd, in packet_splitter
-rw-r--r--usrp2/gpif/Makefile.srcs1
-rw-r--r--usrp2/gpif/gpif.v13
-rw-r--r--usrp2/gpif/gpif_rd.v11
-rw-r--r--usrp2/gpif/gpif_tb.v98
-rw-r--r--usrp2/gpif/packet_splitter.v79
5 files changed, 188 insertions, 14 deletions
diff --git a/usrp2/gpif/Makefile.srcs b/usrp2/gpif/Makefile.srcs
index d7eaf9fca..bf2b7f74d 100644
--- a/usrp2/gpif/Makefile.srcs
+++ b/usrp2/gpif/Makefile.srcs
@@ -10,4 +10,5 @@ gpif.v \
gpif_wr.v \
gpif_rd.v \
packet_reframer.v \
+packet_splitter.v \
))
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v
index 052a66bff..2a9fd901e 100644
--- a/usrp2/gpif/gpif.v
+++ b/usrp2/gpif/gpif.v
@@ -85,8 +85,8 @@ module gpif
wire [35:0] rx36_data, rx_data;
wire rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy;
- wire [18:0] rx19_data;
- wire rx19_src_rdy, rx19_dst_rdy;
+ wire [18:0] rx19_data, splt_data;
+ wire rx19_src_rdy, rx19_dst_rdy, splt_src_rdy, splt_dst_rdy;
wire [18:0] resp_data, resp_int1, resp_int2;
wire resp_src_rdy, resp_dst_rdy;
wire resp_src_rdy_int1, resp_dst_rdy_int1, resp_src_rdy_int2, resp_dst_rdy_int2;
@@ -96,18 +96,23 @@ module gpif
.datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy),
.dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
- fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // FIXME Endianness?
+ fifo36_to_fifo19 #(.LE(1)) f36_to_f19
(.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
.f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
.f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) );
+ packet_splitter #(.FRAME_LEN(256)) packet_splitter
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy),
+ .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy));
+
gpif_rd gpif_rd
(.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
.gpif_data(gpif_d_out), .gpif_rd(RD), .gpif_ep(EP),
.gpif_empty_d(DE), .gpif_empty_c(CE),
.sys_clk(fifo_clk), .sys_rst(fifo_rst),
- .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy),
+ .data_i(splt_data), .src_rdy_i(splt_src_rdy), .dst_rdy_o(splt_dst_rdy),
.resp_i(resp_data), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy),
.debug(debug_rd) );
diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v
index e79b275b3..ed0721a36 100644
--- a/usrp2/gpif/gpif_rd.v
+++ b/usrp2/gpif/gpif_rd.v
@@ -32,8 +32,7 @@ module gpif_rd
.arst(sys_rst));
reg [7:0] packet_count;
- reg do_padding;
- wire consume_data_line = gpif_rd & ~gpif_ep & ~read_count[8] & ~do_padding;
+ wire consume_data_line = gpif_rd & ~gpif_ep & ~read_count[8];
wire produce_eop = src_rdy_int & dst_rdy_int & data_int[17];
wire consume_sop = consume_data_line & final_rdy_data & data_o[16];
wire consume_eop = consume_data_line & final_rdy_data & data_o[17];
@@ -54,14 +53,6 @@ module gpif_rd
always @(negedge gpif_clk)
if(gpif_rst)
- do_padding <= 0;
- else if(~gpif_rd)
- do_padding <= 0;
- else if(consume_eop)
- do_padding <= 1;
-
- always @(negedge gpif_clk)
- if(gpif_rst)
gpif_empty_d <= 1;
else
gpif_empty_d <= ~|packet_count;
diff --git a/usrp2/gpif/gpif_tb.v b/usrp2/gpif/gpif_tb.v
new file mode 100644
index 000000000..1cb84e9fb
--- /dev/null
+++ b/usrp2/gpif/gpif_tb.v
@@ -0,0 +1,98 @@
+
+module gpif_tb();
+
+ reg sys_clk = 0;
+ reg sys_rst = 1;
+ reg gpif_clk = 0;
+ reg gpif_rst = 1;
+
+ reg [15:0] gpif_data;
+ reg WR = 0, EP = 0;
+
+ wire CF, DF;
+
+ wire gpif_full_d, gpif_full_c;
+ wire [18:0] data_o, ctrl_o;
+ wire src_rdy, dst_rdy;
+ wire ctrl_src_rdy, ctrl_dst_rdy;
+
+ assign ctrl_dst_rdy = 1;
+ assign dst_rdy = 1;
+
+ initial $dumpfile("gpif_tb.vcd");
+ initial $dumpvars(0,gpif_tb);
+
+ initial #1000 gpif_rst = 0;
+ initial #1000 sys_rst = 0;
+ always #64 gpif_clk <= ~gpif_clk;
+ always #47.9 sys_clk <= ~sys_clk;
+
+ wire [18:0] data_int;
+ wire src_rdy_int, dst_rdy_int;
+
+ gpif_wr gpif_write
+ (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+ .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP),
+ .gpif_full_d(DF), .gpif_full_c(CF),
+
+ .sys_clk(sys_clk), .sys_rst(sys_rst),
+ .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int),
+ .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) );
+
+ packet_reframer tx_packet_reframer
+ (.clk(sys_clk), .reset(sys_rst), .clear(0),
+ .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
+ .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+ packet_splitter #(.FRAME_LEN(256)) rx_packet_splitter
+ (.clk(sys_clk), .reset(sys_rst), .clear(0),
+ .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+ .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+ always @(posedge sys_clk)
+ if(ctrl_src_rdy & ctrl_dst_rdy)
+ $display("CTRL: %x",ctrl_o);
+
+ always @(posedge sys_clk)
+ if(src_rdy & dst_rdy)
+ begin
+ if(data_o[16])
+ $display("<-------- DATA SOF--------->");
+ $display("DATA: %x",data_o);
+ if(data_o[17])
+ $display("<-------- DATA EOF--------->");
+ end
+
+ initial
+ begin
+ #10000;
+ repeat (1)
+ begin
+ WR <= 1;
+ gpif_data <= 10; // Length
+ @(posedge gpif_clk);
+ gpif_data <= 16'h00;
+ @(posedge gpif_clk);
+ repeat(254)
+ begin
+ gpif_data <= gpif_data + 1;
+ @(posedge gpif_clk);
+ end
+ WR <= 0;
+ repeat (20)
+ @(posedge gpif_clk);
+ WR <= 1;
+ gpif_data <= 16'h5;
+ @(posedge gpif_clk);
+ repeat(254)
+ begin
+ gpif_data <= gpif_data - 1;
+ @(posedge gpif_clk);
+ end
+ end
+ end // initial begin
+
+ initial #100000 $finish;
+
+
+endmodule // gpif_tb
diff --git a/usrp2/gpif/packet_splitter.v b/usrp2/gpif/packet_splitter.v
new file mode 100644
index 000000000..43515dd8b
--- /dev/null
+++ b/usrp2/gpif/packet_splitter.v
@@ -0,0 +1,79 @@
+
+// Split vita packets longer than one GPIF frame, add padding on short frames
+
+module packet_splitter
+ #(parameter FRAME_LEN=256)
+ (input clk, input reset, input clear,
+ input [18:0] data_i,
+ input src_rdy_i,
+ output dst_rdy_o,
+ output [18:0] data_o,
+ output src_rdy_o,
+ input dst_rdy_i);
+
+ reg [1:0] state;
+ reg [15:0] length;
+ reg [15:0] frame_len;
+
+ localparam PS_IDLE = 0;
+ localparam PS_FRAME = 1;
+ localparam PS_NEW_FRAME = 2;
+ localparam PS_PAD = 3;
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= PS_IDLE;
+ else
+ case(state)
+ PS_IDLE :
+ if(src_rdy_i & dst_rdy_i)
+ begin
+ length <= { data_i[14:0],1'b0};
+ frame_len <= FRAME_LEN;
+ state <= PS_FRAME;
+ end
+ PS_FRAME :
+ if(src_rdy_i & dst_rdy_i)
+ if(frame_len == 0)
+ if(length == 0)
+ state <= PS_IDLE;
+ else
+ begin
+ state <= PS_NEW_FRAME;
+ frame_len <= FRAME_LEN;
+ length <= length - 1;
+ end
+ else
+ if(length == 0)
+ begin
+ frame_len <= frame_len - 1;
+ state <= PS_PAD;
+ end
+ PS_NEW_FRAME :
+ if(src_rdy_i & dst_rdy_i)
+ begin
+ frame_len <= frame_len - 1;
+ state <= PS_FRAME;
+ end
+ PS_PAD :
+ if(dst_rdy_i)
+ if(frame_len == 0)
+ state <= PS_IDLE;
+ else
+ frame_len <= frame_len - 1;
+
+ endcase // case (state)
+
+
+
+ assign dst_rdy_o = dst_rdy_i & (state != PS_PAD);
+ assign src_rdy_o = src_rdy_i | (state == PS_PAD);
+
+ wire occ_out = 0;
+ wire eof_out = (frame_len == 0) & (state != PS_IDLE);
+ wire sof_out = (state == PS_IDLE) | (state == PS_NEW_FRAME);
+
+ wire [15:0] data_out = data_i[15:0];
+ assign data_o = {occ_out, eof_out, sof_out, data_out};
+
+endmodule // packet_splitter