ISE chokes on the pure verilog version so we use the macro

1 files changed, 49 insertions, 4 deletions

diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v
index 3fa43114f..e10321959 100644
--- a/usrp2/control_lib/ram_2port_mixed_width.v
+++ b/usrp2/control_lib/ram_2port_mixed_width.v
@@ -1,5 +1,3 @@
-
-
 module ram_2port_mixed_width
   #(parameter AWIDTH=9)
     (input clk16,
@@ -7,14 +5,58 @@ module ram_2port_mixed_width
      input we16,
      input [10:0] addr16,
      input [15:0] di16,
-     output reg [15:0] do16,
+     output [15:0] do16,
      
      input clk32,
      input en32,
      input we32,
      input [9:0] addr32,
      input [31:0] di32,
-     output reg [31:0] do32);
+     output [31:0] do32);
+
+   RAMB16BWER #(.DATA_WIDTH_A(18),  // Valid values are 0, 1, 2, 4, 9, 18, or 36
+		.DATA_WIDTH_B(36),  // Valid values are 0, 1, 2, 4, 9, 18, or 36
+		.DOA_REG(0), // Specifies to enable=1/disable=0 port A output registers
+		.DOB_REG(0), // Specifies to enable=1/disable=0 port B output registers
+		.INIT_A(36'h000000000),  // Initial values on A output port
+		.INIT_B(36'h000000000),  // Initial values on B output port
+		.RSTTYPE("SYNC"),  // Specifes reset type to be "SYNC" or "ASYNC" 
+		.SIM_COLLISION_CHECK("ALL"),  // Collision check enable "ALL", "WARNING_ONLY", 
+                //   "GENERATE_X_ONLY" or "NONE" 
+		.SRVAL_A(36'h000000000), // Set/Reset value for A port output
+		.SRVAL_B(36'h000000000),  // Set/Reset value for B port output
+		.WRITE_MODE_A("WRITE_FIRST"),  // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" 
+		.WRITE_MODE_B("WRITE_FIRST"))  // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" 
+   RAMB16BWER_inst (.DOA(do16),      // 32-bit A port data output
+		    .DOB(do32),      // 32-bit B port data output
+		    .DOPA(),    // 4-bit A port parity data output
+		    .DOPB(),    // 4-bit B port parity data output
+		    .ADDRA(addr16),  // 14-bit A port address input
+		    .ADDRB(addr32),  // 14-bit B port address input
+		    .CLKA(clk16),    // 1-bit A port clock input
+		    .CLKB(clk32),    // 1-bit B port clock input
+		    .DIA(di16),      // 32-bit A port data input
+		    .DIB(di32),      // 32-bit B port data input
+		    .DIPA(0),    // 4-bit A port parity data input
+		    .DIPB(0),    // 4-bit B port parity data input
+		    .ENA(en16),      // 1-bit A port enable input
+		    .ENB(en32),      // 1-bit B port enable input
+		    .REGCEA(0), // 1-bit A port output register enable input
+		    .REGCEB(0), // 1-bit B port output register enable input
+		    .RSTA(0),    // 1-bit A port reset input
+		    .RSTB(0),    // 1-bit B port reset input
+		    .WEA({2{we16}}),      // 4-bit A port write enable input
+		    .WEB({4{we32}})       // 4-bit B port write enable input
+		    );
+   
+endmodule // ram_2port_mixed_width
+
+
+
+   
+// ISE 10.1.03 chokes on the following
+   
+/*
    
    reg [31:0] 	       ram [(1<<AWIDTH)-1:0];
    integer 	       i;
@@ -42,3 +84,6 @@ module ram_2port_mixed_width
        end
 
 endmodule // ram_2port_mixed_width
+
+ 
+ */