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| author | Josh Blum <josh@joshknows.com> | 2012-01-30 23:04:31 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-01-30 23:04:31 -0800 |
| commit | 531a7910c22dce40de5ddccee0cb05275b73fe32 (patch) | |
| tree | 74f1c6558737a8e7c31a6ded50b56fc4cf732209 | |
| parent | 327c25864e3d09fdc34fe9f438dded1329b0c65c (diff) | |
| download | uhd-531a7910c22dce40de5ddccee0cb05275b73fe32.tar.gz uhd-531a7910c22dce40de5ddccee0cb05275b73fe32.tar.bz2 uhd-531a7910c22dce40de5ddccee0cb05275b73fe32.zip | |
dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_buffering
| -rw-r--r-- | usrp2/sdr_lib/dspengine_8to16.v | 10 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 11 |
2 files changed, 13 insertions, 8 deletions
diff --git a/usrp2/sdr_lib/dspengine_8to16.v b/usrp2/sdr_lib/dspengine_8to16.v index 66568bc12..7319451e5 100644 --- a/usrp2/sdr_lib/dspengine_8to16.v +++ b/usrp2/sdr_lib/dspengine_8to16.v @@ -132,7 +132,7 @@ module dspengine_8to16 dsp_state <= DSP_READ; write_adr <= write_adr - 1; read_adr <= read_adr - 1; - new_header[15:0] <= write_adr; // length = addr of trailer + 1 + new_header[15:0] <= write_adr + (1 - HEADER_OFFSET); // length = addr of trailer + 1 end DSP_READ : @@ -145,7 +145,7 @@ module dspengine_8to16 begin write_adr <= write_adr - 1; odd <= 0; - if(write_adr == (hdr_length_reg+1)) + if(write_adr == (hdr_length_reg+HEADER_OFFSET)) dsp_state <= DSP_WRITE_HEADER; else if(odd) dsp_state <= DSP_READ; @@ -156,7 +156,7 @@ module dspengine_8to16 DSP_WRITE_0 : begin write_adr <= write_adr - 1; - if(write_adr == (hdr_length_reg+1)) + if(write_adr == (hdr_length_reg+HEADER_OFFSET)) dsp_state <= DSP_WRITE_HEADER; else dsp_state <= DSP_READ; @@ -167,8 +167,8 @@ module dspengine_8to16 DSP_DONE : begin - read_adr <= 1; - write_adr <= 1; + read_adr <= HEADER_OFFSET; + write_adr <= HEADER_OFFSET; dsp_state <= DSP_IDLE; end endcase // case (dsp_state) diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 8002eae83..189876015 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -64,8 +64,8 @@ module vita_tx_chain wire [FIFOSIZE-1:0] access_adr, access_len; wire access_we, access_stb, access_ok, access_done, access_skip_read; wire [35:0] dsp_to_buf, buf_to_dsp; - wire [35:0] tx_data_int2; - wire tx_src_rdy_int2, tx_dst_rdy_int2; + wire [35:0] tx_data_int1, tx_data_int2; + wire tx_src_rdy_int1, tx_dst_rdy_int1, tx_src_rdy_int2, tx_dst_rdy_int2; double_buffer #(.BUF_SIZE(FIFOSIZE)) db (.clk(clk),.reset(reset),.clear(clear), @@ -74,7 +74,7 @@ module vita_tx_chain .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp), .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), - .data_o(tx_data_int2), .src_rdy_o(tx_src_rdy_int2), .dst_rdy_i(tx_dst_rdy_int2)); + .data_o(tx_data_int1), .src_rdy_o(tx_src_rdy_int1), .dst_rdy_i(tx_dst_rdy_int1)); dspengine_8to16 #(.BASE(BASE+6), .BUF_SIZE(FIFOSIZE), .HEADER_OFFSET(USE_TRANS_HEADER)) dspengine_8to16 (.clk(clk),.reset(reset),.clear(clear), @@ -83,6 +83,11 @@ module vita_tx_chain .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf)); + fifo_cascade #(.WIDTH(36), .SIZE(9)) post_engine_buffering( + .clk(clk), .reset(reset), .clear(clear), + .datain(tx_data_int1), .src_rdy_i(tx_src_rdy_int1), .dst_rdy_o(tx_dst_rdy_int1), + .dataout(tx_data_int2), .src_rdy_o(tx_src_rdy_int2), .dst_rdy_i(tx_dst_rdy_int2)); + vita_tx_deframer #(.BASE(BASE), .MAXCHAN(MAXCHAN), .USE_TRANS_HEADER(USE_TRANS_HEADER)) |