added 16-bit wide atr controller

settings_bus_16 now handles variable address window sizes
split ctrl of nsgpio into ctrl (selector) and debug bits

5 files changed, 117 insertions, 47 deletions

diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v
new file mode 100644
index 000000000..3d8b5b1e9
--- /dev/null
+++ b/usrp2/control_lib/atr_controller16.v
@@ -0,0 +1,60 @@
+
+// Automatic transmit/receive switching of control pins to daughterboards
+// Store everything in registers for now, but could use a RAM for more
+// complex state machines in the future
+
+module atr_controller16
+  (input clk_i, input rst_i,
+   input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o,
+   input we_i, input stb_i, input cyc_i, output reg ack_o,
+   input run_rx, input run_tx, input [31:0] master_time,
+   output [31:0] ctrl_lines);
+   
+   reg [3:0] state;
+   reg [31:0] atr_ram [0:15];  // DP distributed RAM
+
+   wire [3:0] sel_int = { (sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]),
+			  (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1]) };
+   
+   // WB Interface
+   always @(posedge clk_i)
+     if(we_i & stb_i & cyc_i)
+       begin
+	  if(sel_int[3])
+	    atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8];
+	  if(sel_int[2])
+	    atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0];
+	  if(sel_int[1])
+	    atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8];
+	  if(sel_int[0])
+	    atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
+       end // if (we_i & stb_i & cyc_i)
+
+   always @(posedge clk_i)
+     dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0];
+   
+   always @(posedge clk_i)
+     ack_o <= stb_i & cyc_i & ~ack_o;
+
+   // Control side of DP RAM
+   assign     ctrl_lines = atr_ram[state];
+
+   // Put a more complex state machine with time delays and multiple states here
+   //  if daughterboard requires more complex sequencing
+   localparam ATR_IDLE = 4'd0;
+   localparam ATR_TX = 4'd1;
+   localparam ATR_RX = 4'd2;
+   localparam ATR_FULL_DUPLEX = 4'd3;
+   
+   always @(posedge clk_i)
+     if(rst_i)
+       state <= ATR_IDLE;
+     else
+       case ({run_rx,run_tx})
+	 2'b00 : state <= ATR_IDLE;
+	 2'b01 : state <= ATR_TX;
+	 2'b10 : state <= ATR_RX;
+	 2'b11 : state <= ATR_FULL_DUPLEX;
+       endcase // case({run_rx,run_tx})
+   
+endmodule // atr_controller16
diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v
index 6847bb4a9..d6d7dcf56 100644
--- a/usrp2/control_lib/nsgpio16LE.v
+++ b/usrp2/control_lib/nsgpio16LE.v
@@ -43,10 +43,7 @@ module nsgpio16LE
    inout [31:0] gpio
    );
 
-   reg [63:0] 	ctrl;
-   reg [31:0] 	line;
-   reg [31:0] 	lgpio;               // LatchedGPIO pins
-   reg [31:0] 	ddr;
+   reg [31:0] 	ctrl, line, ddr, dbg, lgpio;
    
    wire 	wb_acc = cyc_i & stb_i;            // WISHBONE access
    wire 	wb_wr  = wb_acc & we_i;            // WISHBONE write access
@@ -54,8 +51,10 @@ module nsgpio16LE
    always @(posedge clk_i or posedge rst_i)
      if (rst_i)
        begin
-          ctrl <= 64'h0;
-          line <= 0;
+          ctrl <= 32'h0;
+          line <= 32'h0;
+	  ddr <= 32'h0;
+	  dbg <= 32'h0;
        end
      else if (wb_wr)
        case( adr_i[3:1] )
@@ -72,9 +71,9 @@ module nsgpio16LE
 	 3'b101 :
 	   ctrl[31:16] <= dat_i;
 	 3'b110 :
-	   ctrl[47:32] <= dat_i;
+	   dbg[15:0] <= dat_i;
 	 3'b111 :
-	   ctrl[63:48] <= dat_i;
+	   dbg[31:16] <= dat_i;
        endcase // case ( adr_i[3:1] )
    
    always @(posedge clk_i)
@@ -92,9 +91,9 @@ module nsgpio16LE
        3'b101 :
 	 dat_o <= ctrl[31:16];
        3'b110 :
-	 dat_o <= ctrl[47:32];
+	 dat_o <= dbg[15:0];
        3'b111 :
-	 dat_o <= ctrl[63:48];
+	 dat_o <= dbg[31:16];
      endcase // case (adr_i[3:1])
    
    
@@ -114,8 +113,8 @@ module nsgpio16LE
    
    always @(ctrl or line or debug_1 or debug_0 or atr)
      for(n=0;n<32;n=n+1)
-       igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : 
-			     (ctrl[2*n] ?  atr[n] : line[n]) )
+       igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : 
+			     (ctrl[n] ?  atr[n] : line[n]) )
 	 : 1'bz;
    
    assign     gpio = igpio;
diff --git a/usrp2/control_lib/settings_bus_16LE.v b/usrp2/control_lib/settings_bus_16LE.v
index fbef9b1c9..76061e9e0 100644
--- a/usrp2/control_lib/settings_bus_16LE.v
+++ b/usrp2/control_lib/settings_bus_16LE.v
@@ -5,7 +5,7 @@
 // The setting regs are strobed when the high 16 bits are written
 
 module settings_bus_16LE
-  #(parameter AWIDTH=16)
+  #(parameter AWIDTH=16, RWIDTH=8)
     (input wb_clk, 
      input wb_rst, 
      input [AWIDTH-1:0] wb_adr_i,
@@ -28,7 +28,7 @@ module settings_bus_16LE
        end
      else if(wb_we_i & wb_stb_i)
        begin
-	  addr <= wb_adr_i[9:2];
+	  addr <= wb_adr_i[RWIDTH+1:2];  // Zero pad high bits
 	  if(wb_adr_i[1])
 	    begin
 	       stb_int <= 1'b1;     // We now have both halves
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
index 2b78b21bd..a0f921485 100644
--- a/usrp2/top/u1e/Makefile
+++ b/usrp2/top/u1e/Makefile
@@ -54,7 +54,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 export SOURCE_ROOT := ../../../
 export SOURCES := \
 control_lib/CRC16_D16.v \
-control_lib/atr_controller.v \
+control_lib/atr_controller16.v \
 control_lib/bin2gray.v \
 control_lib/dcache.v \
 control_lib/decoder_3_8.v \
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index f2415d7e1..e692cbc3d 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -147,48 +147,52 @@ module u1e_core
       .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
       .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) );
 
-   assign s6_ack = 0;   assign s7_ack = 0;
+   assign s7_ack = 0;
    assign s8_ack = 0;   assign s9_ack = 0;   assign sa_ack = 0;   assign sb_ack = 0;
    assign sc_ack = 0;   assign sd_ack = 0;   assign se_ack = 0;   assign sf_ack = 0;
 
    // /////////////////////////////////////////////////////////////////////////////////////
    // Slave 0, Misc LEDs, Switches, controls
    
-   reg [15:0] 	 reg_fast, reg_slow;
-   localparam REG_FAST = 7'd4;
-   localparam REG_SWITCHES = 7'd6;
-   localparam REG_GPIOS = 7'd8;
-   localparam REG_CGEN_ST = 7'd9;
-   localparam REG_CGEN_CTRL = 7'd10;
+   reg [15:0] 	 reg_leds, reg_cgen_ctrl, reg_test;
    
-   reg [3:0] 	 reg_gpios;
-   
-   always @(posedge wb_clk)
-     if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_FAST))
-       reg_fast <= s0_dat_mosi;
-
-   always @(posedge wb_clk)
-     if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_GPIOS))
-       reg_gpios <= s0_dat_mosi;
-
-   reg [1:0] 	 reg_cgen_ctrls;
+   localparam REG_LEDS = 7'd0;      // out
+   localparam REG_SWITCHES = 7'd2;  // in
+   localparam REG_CGEN_CTRL = 7'd4; // out
+   localparam REG_CGEN_ST = 7'd6;   // in
+   localparam REG_TEST = 7'd8;      // out
    
    always @(posedge wb_clk)
      if(wb_rst)
-       reg_cgen_ctrls <= 2'b11;
-     else if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_CGEN_CTRL))
-       reg_cgen_ctrls <= s0_dat_mosi;
+       begin
+	  reg_leds <= 0;
+	  reg_cgen_ctrl <= 2'b11;
+	  reg_test <= 0;
+       end
+     else
+       if(s0_cyc & s0_stb & s0_we) 
+	 case(s0_adr[6:0])
+	   REG_LEDS :
+	     reg_leds <= s0_dat_mosi;
+	   REG_CGEN_CTRL :
+	     reg_cgen_ctrl <= s0_dat_mosi;
+	   REG_TEST :
+	     reg_test <= s0_dat_mosi;
+	 endcase // case (s0_adr[6:0])
    
-   assign {cgen_sync_b, cgen_ref_sel} = reg_cgen_ctrls;
+   assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds;  // LEDs are arranged funny on board
+   assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
+   assign { rx_overrun, tx_undderun } = reg_test;
    
-   assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast : 
+   assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : 
 			(s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} :
+			(s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
 			(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
+			(s0_adr[6:0] == REG_TEST) ? reg_test :
 			16'hBEEF;
+   
    assign s0_ack = s0_stb & s0_cyc;
 
-   assign { rx_overrun, tx_underrun } = reg_gpios;
-
    // /////////////////////////////////////////////////////////////////////////////////////
    // Slave 1, UART
    //    depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock
@@ -196,7 +200,7 @@ module u1e_core
    simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart 
      (.clk_i(wb_clk),.rst_i(wb_rst),
       .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack),
-      .adr_i(s1_adr[4:2]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso),
+      .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso),
       .rx_int_o(),.tx_int_o(),
       .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o());
 
@@ -246,16 +250,25 @@ module u1e_core
    wire [7:0] 	set_addr;
    wire [31:0] 	set_data;
    wire 	set_stb;
-   
-   settings_bus_16LE settings_bus_16LE
+
+   // only have 32 regs, 32 bits each with current setup...
+   settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE
      (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi),
       .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack),
       .strobe(set_stb),.addr(set_addr),.data(set_data) );
    
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // Debug Pins
+   // /////////////////////////////////////////////////////////////////////////
+   // ATR Controller -- Slave #6
+
+   atr_controller16 atr_controller16
+     (.clk_i(wb_clk), .rst_i(wb_rst),
+      .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso),
+      .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack),
+      .run_rx(), .run_tx(), .master_time(0), .ctrl_lines(atr_lines));
    
+   // /////////////////////////////////////////////////////////////////////////////////////
    // Debug circuitry
+
    assign debug_clk = { EM_CLK, clk_fpga };
    assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
 		    { EM_D } };
@@ -263,6 +276,4 @@ module u1e_core
    assign debug_gpio_0 = { debug_gpmc };
    assign debug_gpio_1 = { debug_txd, debug_rxd };
    
-   assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast;  // LEDs are arranged funny on board
-   
 endmodule // u1e_core