b100: fix slave fifo data xfer exit condition

When exiting the read/write data state,
when the transfer count maxes out/peaks,
the fifo read/write signals were getting this
condition the cycle after with the state change.

2 files changed, 5 insertions, 5 deletions

diff --git a/usrp2/gpif/slave_fifo.v b/usrp2/gpif/slave_fifo.v
index b1d642fca..e75f28913 100644
--- a/usrp2/gpif/slave_fifo.v
+++ b/usrp2/gpif/slave_fifo.v
@@ -150,7 +150,7 @@ module slave_fifo
 
          STATE_DATA_RX:
             begin
-                if(data_rx_src_rdy && data_rx_dst_rdy && (transfer_count != data_transfer_size))
+                if(data_rx_src_rdy && data_rx_dst_rdy)
                     transfer_count <= transfer_count + 1;
                 else
                     state <= STATE_IDLE;
@@ -170,7 +170,7 @@ module slave_fifo
             
          STATE_DATA_TX:
             begin
-                if(data_tx_dst_rdy && data_tx_src_rdy && (transfer_count != data_transfer_size))
+                if(data_tx_dst_rdy && data_tx_src_rdy)
                     transfer_count <= transfer_count + 1;
                 else
                     state <= STATE_IDLE;
@@ -197,8 +197,8 @@ module slave_fifo
    // fifo signal assignments and enables
 
    //enable fifos
-   assign data_rx_dst_rdy = (state == STATE_DATA_RX) && ~FX2_DF;
-   assign data_tx_src_rdy = (state == STATE_DATA_TX) && ~FX2_DE;
+   assign data_rx_dst_rdy = (state == STATE_DATA_RX) && ~FX2_DF && (transfer_count != data_transfer_size);
+   assign data_tx_src_rdy = (state == STATE_DATA_TX) && ~FX2_DE && (transfer_count != data_transfer_size);
    assign ctrl_rx_dst_rdy = (state == STATE_CTRL_RX) && ~FX2_CF;
    assign ctrl_tx_src_rdy = (state == STATE_CTRL_TX) && ~FX2_CE;
 
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index 26714b669..09b7e11f1 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -413,7 +413,7 @@ module u1plus_core
    // Readback mux 32 -- Slave #7
 
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd9, 16'd1}; //major, minor
+   localparam compat_num = {16'd9, 16'd2}; //major, minor
 
    wire [31:0] reg_test32;