Moved some misc setting registers into host.

3 files changed, 28 insertions, 15 deletions

diff --git a/firmware/microblaze/lib/u2_init.c b/firmware/microblaze/lib/u2_init.c
index b4fbb9e88..6809101c0 100644
--- a/firmware/microblaze/lib/u2_init.c
+++ b/firmware/microblaze/lib/u2_init.c
@@ -46,8 +46,6 @@ get_hw_rev(void)
 bool
 u2_init(void)
 {
-  dsp_rx_regs->gpio_stream_enable = 0; // I, Q LSBs come from DSP
-
   hal_io_init();
 
   // init spi, so that we can switch over to the high-speed clock
@@ -60,14 +58,6 @@ u2_init(void)
   // set up the default clocks
   clocks_init();
 
-  // clocks_enable_test_clk(true,1);
-
-  // Enable ADCs
-  output_regs->adc_ctrl = ADC_CTRL_ON;
-
-  // Set up serdes
-  output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN);
-
   pic_init();	// progammable interrupt controller
   bp_init();	// buffer pool
   
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index 48aeb2a62..2c8fd2df4 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -63,6 +63,13 @@ void usrp2_impl::mboard_init(void){
         boost::uint16_t data = ad9777_regs.get_write_reg(addr);
         _iface->transact_spi(SPI_SS_AD9777, spi_config_t::EDGE_RISE, data, 16, false /*no rb*/);
     }
+
+    //enable ADCs
+    _iface->poke32(FR_MISC_CTRL_ADC, FRF_MISC_CTRL_ADC_ON);
+
+    //set up serdes
+    _iface->poke32(FR_MISC_CTRL_SERDES, FRF_MISC_CTRL_SERDES_ENABLE | FRF_MISC_CTRL_SERDES_RXEN);
+
 }
 
 void usrp2_impl::init_clock_config(void){
@@ -97,9 +104,9 @@ void usrp2_impl::update_clock_config(void){
 
     //clock source ref 10mhz
     switch(_clock_config.ref_source){
-    case clock_config_t::REF_INT : _iface->poke32(FR_CLOCK_CONTROL, 0x10); break;
-    case clock_config_t::REF_SMA : _iface->poke32(FR_CLOCK_CONTROL, 0x1C); break;
-    case clock_config_t::REF_MIMO: _iface->poke32(FR_CLOCK_CONTROL, 0x15); break;
+    case clock_config_t::REF_INT : _iface->poke32(FR_MISC_CTRL_CLOCK, 0x10); break;
+    case clock_config_t::REF_SMA : _iface->poke32(FR_MISC_CTRL_CLOCK, 0x1C); break;
+    case clock_config_t::REF_MIMO: _iface->poke32(FR_MISC_CTRL_CLOCK, 0x15); break;
     default: throw std::runtime_error("usrp2: unhandled clock configuration reference source");
     }
 
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 67a342217..feeccaa34 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -64,7 +64,23 @@
 /////////////////////////////////////////////////
 // Misc Control
 ////////////////////////////////////////////////
-#define FR_CLOCK_CONTROL _SR_ADDR(0)
+#define FR_MISC_CTRL_CLOCK           _SR_ADDR(0)
+#define FR_MISC_CTRL_SERDES          _SR_ADDR(1)
+#define FR_MISC_CTRL_ADC             _SR_ADDR(2)
+#define FR_MISC_CTRL_LEDS            _SR_ADDR(3)
+#define FR_MISC_CTRL_PHY             _SR_ADDR(4) // LSB is reset line to eth phy
+#define FR_MISC_CTRL_DBG_MUX         _SR_ADDR(5)
+#define FR_MISC_CTRL_RAM_PAGE        _SR_ADDR(6) // FIXME should go somewhere else...
+#define FR_MISC_CTRL_FLUSH_ICACHE    _SR_ADDR(7) // Flush the icache
+#define FR_MISC_CTRL_LED_SRC         _SR_ADDR(8) // HW or SW control for LEDs
+
+#define FRF_MISC_CTRL_SERDES_ENABLE 8
+#define FRF_MISC_CTRL_SERDES_PRBSEN 4
+#define FRF_MISC_CTRL_SERDES_LOOPEN 2
+#define FRF_MISC_CTRL_SERDES_RXEN   1
+
+#define FRF_MISC_CTRL_ADC_ON  0x0F
+#define FRF_MISC_CTRL_ADC_OFF 0x00
 
 /////////////////////////////////////////////////
 // VITA49 64 bit time (write only)
@@ -208,7 +224,7 @@
 #define FR_ATR_FULL_RXSIDE  FR_ATR_BASE + 14
 
 ///////////////////////////////////////////////////
-// ATR Controller, Slave 11
+// VITA RX CTRL regs
 ///////////////////////////////////////////////////
 // The following 3 are logically a single command register.
 // They are clocked into the underlying fifo when time_ticks is written.