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authorMatt Ettus <matt@ettus.com>2009-09-10 21:52:06 -0700
committerMatt Ettus <matt@ettus.com>2009-09-10 21:52:06 -0700
commit2f3e0eefe01b61f8e5e12d2ceef6990abb8a1ff3 (patch)
tree38845a43e869454ed88fc68d26c56b7aa3b49e97
parent38e0c588af094e7f809ad73981a3ba002d2c936d (diff)
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More xilinx fifos, more clean up of our fifos
Diffstat
-rw-r--r--control_lib/cascadefifo2.v56
-rw-r--r--control_lib/newfifo/fifo18_to_ll8.v58
-rw-r--r--control_lib/newfifo/fifo_2clock.v42
-rw-r--r--coregen/fifo_xlnx_16x19_2clk.ngc3
-rw-r--r--coregen/fifo_xlnx_16x19_2clk.v169
-rw-r--r--coregen/fifo_xlnx_16x19_2clk.veo53
-rw-r--r--coregen/fifo_xlnx_16x19_2clk.xco82
-rw-r--r--coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso3
-rw-r--r--coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt103
-rw-r--r--coregen/fifo_xlnx_16x19_2clk_flist.txt8
-rw-r--r--coregen/fifo_xlnx_16x19_2clk_readme.txt39
-rw-r--r--coregen/fifo_xlnx_16x19_2clk_xmdf.tcl68
12 files changed, 555 insertions, 129 deletions
diff --git a/control_lib/cascadefifo2.v b/control_lib/cascadefifo2.v
deleted file mode 100644
index 984cc46e6..000000000
--- a/control_lib/cascadefifo2.v
+++ /dev/null
@@ -1,56 +0,0 @@
-
-
-// This FIFO exists to provide an intermediate point for the data on its
-// long trek from one RAM (in the buffer pool) to another (in the longfifo)
-// The shortfifo is more flexible in its placement since it is based on
-// distributed RAM
-
-// This one has the shortfifo on both the in and out sides.
-module cascadefifo2
- #(parameter WIDTH=32, SIZE=9)
- (input clk, input rst,
- input [WIDTH-1:0] datain,
- output [WIDTH-1:0] dataout,
- input read,
- input write,
- input clear,
- output full,
- output empty,
- output [15:0] space,
- output [15:0] occupied);
-
- wire [WIDTH-1:0] data_int, data_int2;
- wire empty_int, full_int, transfer;
- wire empty_int2, full_int2, transfer2;
- wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied;
- wire [15:0] l_space, l_occupied;
-
- shortfifo #(.WIDTH(WIDTH)) shortfifo
- (.clk(clk),.rst(rst),.clear(clear),
- .datain(datain), .write(write), .full(full),
- .dataout(data_int), .read(transfer), .empty(empty_int),
- .space(s1_space),.occupied(s1_occupied) );
-
- longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
- (.clk(clk),.rst(rst),.clear(clear),
- .datain(data_int), .write(transfer), .full(full_int),
- .dataout(data_int2), .read(transfer2), .empty(empty_int2),
- .space(l_space),.occupied(l_occupied) );
-
- shortfifo #(.WIDTH(WIDTH)) shortfifo2
- (.clk(clk),.rst(rst),.clear(clear),
- .datain(data_int2), .write(transfer2), .full(full_int2),
- .dataout(dataout), .read(read), .empty(empty),
- .space(s2_space),.occupied(s2_occupied) );
-
- assign transfer = ~empty_int & ~full_int;
- assign transfer2 = ~empty_int2 & ~full_int2;
-
- assign space = {11'b0,s1_space} + {11'b0,s2_space} + l_space;
- assign occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + l_occupied;
-
-endmodule // cascadefifo2
-
-
-
-
diff --git a/control_lib/newfifo/fifo18_to_ll8.v b/control_lib/newfifo/fifo18_to_ll8.v
deleted file mode 100644
index 4653244ef..000000000
--- a/control_lib/newfifo/fifo18_to_ll8.v
+++ /dev/null
@@ -1,58 +0,0 @@
-
-module fifo18_to_ll8
- (input clk, input reset, input clear,
- input [35:0] f18_data,
- input f18_src_rdy_i,
- output f18_dst_rdy_o,
-
- output reg [7:0] ll_data,
- output ll_sof_n,
- output ll_eof_n,
- output ll_src_rdy_n,
- input ll_dst_rdy_n);
-
- wire ll_sof, ll_eof, ll_src_rdy;
- assign ll_sof_n = ~ll_sof;
- assign ll_eof_n = ~ll_eof;
- assign ll_src_rdy_n = ~ll_src_rdy;
- wire ll_dst_rdy = ~ll_dst_rdy_n;
-
- wire f18_sof = f18_data[32];
- wire f18_eof = f18_data[33];
- wire f18_occ = f18_data[35:34];
- wire advance, end_early;
- reg [1:0] state;
- assign debug = {29'b0,state};
-
- always @(posedge clk)
- if(reset)
- state <= 0;
- else
- if(advance)
- if(ll_eof)
- state <= 0;
- else
- state <= state + 1;
-
- always @*
- case(state)
- 0 : ll_data = f18_data[31:24];
- 1 : ll_data = f18_data[23:16];
- 2 : ll_data = f18_data[15:8];
- 3 : ll_data = f18_data[7:0];
- default : ll_data = f18_data[31:24];
- endcase // case (state)
-
- assign ll_sof = (state==0) & f18_sof;
- assign ll_eof = f18_eof & (((state==0)&(f18_occ==1)) |
- ((state==1)&(f18_occ==2)) |
- ((state==2)&(f18_occ==3)) |
- (state==3));
-
- assign ll_src_rdy = f18_src_rdy_i;
-
- assign advance = ll_src_rdy & ll_dst_rdy;
- assign f18_dst_rdy_o = advance & ((state==3)|ll_eof);
- assign debug = state;
-
-endmodule // ll8_to_fifo36
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
index 2ada39fb0..07ae090f2 100644
--- a/control_lib/newfifo/fifo_2clock.v
+++ b/control_lib/newfifo/fifo_2clock.v
@@ -16,21 +16,33 @@ module fifo_2clock
assign read = src_rdy_o & dst_rdy_i;
generate
- if(SIZE==9)
- fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
- (.rst(rst),
- .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
- .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
- else if(SIZE==11)
- fifo_xlnx_2Kx36_2clk mac_tx_fifo_2clk
- (.rst(rst),
- .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
- .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
- else if(SIZE==6)
- fifo_xlnx_64x36_2clk mac_tx_fifo_2clk
- (.rst(rst),
- .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
- .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ if(WIDTH==36)
+ if(SIZE==9)
+ fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else if(SIZE==11)
+ fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else if(SIZE==6)
+ fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else
+ fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else if((WIDTH==19)|(WIDTH==18))
+ if(SIZE==4)
+ fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
endgenerate
assign occupied = {{(16-SIZE-1){1'b0}},level_rclk};
diff --git a/coregen/fifo_xlnx_16x19_2clk.ngc b/coregen/fifo_xlnx_16x19_2clk.ngc
new file mode 100644
index 000000000..b12d34d7c
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
+$3f24g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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diff --git a/coregen/fifo_xlnx_16x19_2clk.v b/coregen/fifo_xlnx_16x19_2clk.v
new file mode 100644
index 000000000..1d633384b
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk.v
@@ -0,0 +1,169 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2007 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating
+// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_16x19_2clk(
+ din,
+ rd_clk,
+ rd_en,
+ rst,
+ wr_clk,
+ wr_en,
+ dout,
+ empty,
+ full,
+ rd_data_count,
+ wr_data_count);
+
+
+input [18 : 0] din;
+input rd_clk;
+input rd_en;
+input rst;
+input wr_clk;
+input wr_en;
+output [18 : 0] dout;
+output empty;
+output full;
+output [4 : 0] rd_data_count;
+output [4 : 0] wr_data_count;
+
+// synthesis translate_off
+
+ FIFO_GENERATOR_V4_3 #(
+ .C_COMMON_CLOCK(0),
+ .C_COUNT_TYPE(0),
+ .C_DATA_COUNT_WIDTH(5),
+ .C_DEFAULT_VALUE("BlankString"),
+ .C_DIN_WIDTH(19),
+ .C_DOUT_RST_VAL("0"),
+ .C_DOUT_WIDTH(19),
+ .C_ENABLE_RLOCS(0),
+ .C_FAMILY("spartan3"),
+ .C_FULL_FLAGS_RST_VAL(1),
+ .C_HAS_ALMOST_EMPTY(0),
+ .C_HAS_ALMOST_FULL(0),
+ .C_HAS_BACKUP(0),
+ .C_HAS_DATA_COUNT(0),
+ .C_HAS_INT_CLK(0),
+ .C_HAS_MEMINIT_FILE(0),
+ .C_HAS_OVERFLOW(0),
+ .C_HAS_RD_DATA_COUNT(1),
+ .C_HAS_RD_RST(0),
+ .C_HAS_RST(1),
+ .C_HAS_SRST(0),
+ .C_HAS_UNDERFLOW(0),
+ .C_HAS_VALID(0),
+ .C_HAS_WR_ACK(0),
+ .C_HAS_WR_DATA_COUNT(1),
+ .C_HAS_WR_RST(0),
+ .C_IMPLEMENTATION_TYPE(2),
+ .C_INIT_WR_PNTR_VAL(0),
+ .C_MEMORY_TYPE(2),
+ .C_MIF_FILE_NAME("BlankString"),
+ .C_MSGON_VAL(1),
+ .C_OPTIMIZATION_MODE(0),
+ .C_OVERFLOW_LOW(0),
+ .C_PRELOAD_LATENCY(0),
+ .C_PRELOAD_REGS(1),
+ .C_PRIM_FIFO_TYPE("512x36"),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+ .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+ .C_PROG_EMPTY_TYPE(0),
+ .C_PROG_FULL_THRESH_ASSERT_VAL(15),
+ .C_PROG_FULL_THRESH_NEGATE_VAL(14),
+ .C_PROG_FULL_TYPE(0),
+ .C_RD_DATA_COUNT_WIDTH(5),
+ .C_RD_DEPTH(16),
+ .C_RD_FREQ(1),
+ .C_RD_PNTR_WIDTH(4),
+ .C_UNDERFLOW_LOW(0),
+ .C_USE_DOUT_RST(1),
+ .C_USE_ECC(0),
+ .C_USE_EMBEDDED_REG(0),
+ .C_USE_FIFO16_FLAGS(0),
+ .C_USE_FWFT_DATA_COUNT(1),
+ .C_VALID_LOW(0),
+ .C_WR_ACK_LOW(0),
+ .C_WR_DATA_COUNT_WIDTH(5),
+ .C_WR_DEPTH(16),
+ .C_WR_FREQ(1),
+ .C_WR_PNTR_WIDTH(4),
+ .C_WR_RESPONSE_LATENCY(1))
+ inst (
+ .DIN(din),
+ .RD_CLK(rd_clk),
+ .RD_EN(rd_en),
+ .RST(rst),
+ .WR_CLK(wr_clk),
+ .WR_EN(wr_en),
+ .DOUT(dout),
+ .EMPTY(empty),
+ .FULL(full),
+ .RD_DATA_COUNT(rd_data_count),
+ .WR_DATA_COUNT(wr_data_count),
+ .CLK(),
+ .INT_CLK(),
+ .BACKUP(),
+ .BACKUP_MARKER(),
+ .PROG_EMPTY_THRESH(),
+ .PROG_EMPTY_THRESH_ASSERT(),
+ .PROG_EMPTY_THRESH_NEGATE(),
+ .PROG_FULL_THRESH(),
+ .PROG_FULL_THRESH_ASSERT(),
+ .PROG_FULL_THRESH_NEGATE(),
+ .RD_RST(),
+ .SRST(),
+ .WR_RST(),
+ .ALMOST_EMPTY(),
+ .ALMOST_FULL(),
+ .DATA_COUNT(),
+ .OVERFLOW(),
+ .PROG_EMPTY(),
+ .PROG_FULL(),
+ .VALID(),
+ .UNDERFLOW(),
+ .WR_ACK(),
+ .SBITERR(),
+ .DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/coregen/fifo_xlnx_16x19_2clk.veo b/coregen/fifo_xlnx_16x19_2clk.veo
new file mode 100644
index 000000000..2e9af1efa
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk.veo
@@ -0,0 +1,53 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2007 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_16x19_2clk YourInstanceName (
+ .din(din), // Bus [18 : 0]
+ .rd_clk(rd_clk),
+ .rd_en(rd_en),
+ .rst(rst),
+ .wr_clk(wr_clk),
+ .wr_en(wr_en),
+ .dout(dout), // Bus [18 : 0]
+ .empty(empty),
+ .full(full),
+ .rd_data_count(rd_data_count), // Bus [4 : 0]
+ .wr_data_count(wr_data_count)); // Bus [4 : 0]
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating
+// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/coregen/fifo_xlnx_16x19_2clk.xco b/coregen/fifo_xlnx_16x19_2clk.xco
new file mode 100644
index 000000000..d0f638026
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk.xco
@@ -0,0 +1,82 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Fri Sep 11 04:33:27 2009
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = True
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.3
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_xlnx_16x19_2clk
+CSET data_count=false
+CSET data_count_width=5
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Independent_Clocks_Distributed_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=15
+CSET full_threshold_negate_value=14
+CSET input_data_width=19
+CSET input_depth=16
+CSET output_data_width=19
+CSET output_depth=16
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=5
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=5
+# END Parameters
+GENERATE
+# CRC: 60b85dda
+
diff --git a/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso b/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
new file mode 100644
index 000000000..f1a6f7899
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
@@ -0,0 +1,3 @@
+blkmemdp_v6_2
+blk_mem_gen_v2_6
+fifo_generator_v4_3
diff --git a/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
new file mode 100644
index 000000000..ef33fff67
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
@@ -0,0 +1,103 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="lin64" product="ISE" version="10.1.03">
+
+ <!--The data in this file is primarily intended for consumption by Xilinx tools.
+ The structure and the elements are likely to change over the next few releases.
+ This means code written to parse this file will need to be revisited each subsequent release.-->
+
+ <application stringID="Xst" timeStamp="Thu Sep 10 21:33:06 2009">
+ <section stringID="XST_HDL_SYNTHESIS_REPORT">
+ <item dataType="int" stringID="XST_RAMS" value="1"></item>
+ <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
+ <item dataType="int" stringID="XST_COUNTERS" value="2">
+ <item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
+ </item>
+ <item dataType="int" stringID="XST_REGISTERS" value="32">
+ <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
+ <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
+ <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
+ <item dataType="int" stringID="XST_4BIT_REGISTER" value="11"/>
+ <item dataType="int" stringID="XST_5BIT_REGISTER" value="2"/>
+ </item>
+ <item dataType="int" stringID="XST_XORS" value="28">
+ <item dataType="int" stringID="XST_1BIT_XOR2" value="28"/>
+ </item>
+ </section>
+ <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
+ <item dataType="int" stringID="XST_FSMS" value="1"/>
+ <item dataType="int" stringID="XST_RAMS" value="1"></item>
+ <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
+ <item dataType="int" stringID="XST_COUNTERS" value="2">
+ <item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
+ </item>
+ <item dataType="int" stringID="XST_REGISTERS" value="107">
+ <item dataType="int" stringID="XST_FLIPFLOPS" value="107"/>
+ </item>
+ <item dataType="int" stringID="XST_XORS" value="28">
+ <item dataType="int" stringID="XST_1BIT_XOR2" value="28"/>
+ </item>
+ </section>
+ <section stringID="XST_FINAL_REGISTER_REPORT">
+ <item dataType="int" stringID="XST_REGISTERS" value="126">
+ <item dataType="int" stringID="XST_FLIPFLOPS" value="126"/>
+ </item>
+ </section>
+ <section stringID="XST_PARTITION_REPORT">
+ <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+ <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+ </section>
+ </section>
+ <section stringID="XST_FINAL_REPORT">
+ <section stringID="XST_FINAL_RESULTS">
+ <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc"/>
+ <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
+ <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
+ <item stringID="XST_KEEP_HIERARCHY" value="no"/>
+ </section>
+ <section stringID="XST_DESIGN_STATISTICS">
+ <item stringID="XST_IOS" value="101"/>
+ </section>
+ <section stringID="XST_CELL_USAGE">
+ <item dataType="int" stringID="XST_BELS" value="66">
+ <item dataType="int" stringID="XST_GND" value="1"/>
+ <item dataType="int" stringID="XST_INV" value="2"/>
+ <item dataType="int" stringID="XST_LUT2" value="18"/>
+ <item dataType="int" stringID="XST_LUT2L" value="1"/>
+ <item dataType="int" stringID="XST_LUT3" value="8"/>
+ <item dataType="int" stringID="XST_LUT4" value="30"/>
+ <item dataType="int" stringID="XST_LUT4D" value="3"/>
+ <item dataType="int" stringID="XST_LUT4L" value="3"/>
+ </item>
+ <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="126">
+ <item dataType="int" stringID="XST_FD" value="4"/>
+ <item dataType="int" stringID="XST_FDC" value="40"/>
+ <item dataType="int" stringID="XST_FDCE" value="62"/>
+ <item dataType="int" stringID="XST_FDP" value="10"/>
+ <item dataType="int" stringID="XST_FDPE" value="5"/>
+ </item>
+ <item dataType="int" stringID="XST_RAMS" value="19">
+ <item dataType="int" stringID="XST_RAM16X1D" value="19"/>
+ </item>
+ </section>
+ </section>
+ <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
+ <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
+ <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="96"/>
+ <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="126"/>
+ <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="103"/>
+ <item dataType="int" stringID="XST_NUMBER_USED_AS_LOGIC" value="65"/>
+ <item dataType="int" stringID="XST_NUMBER_USED_AS_RAMS" value="38"/>
+ <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="101"/>
+ <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
+ </section>
+ <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
+ <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+ </section>
+ <section stringID="XST_ERRORS_STATISTICS">
+ <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
+ <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="73"/>
+ <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="10"/>
+ </section>
+ </application>
+
+</document>
diff --git a/coregen/fifo_xlnx_16x19_2clk_flist.txt b/coregen/fifo_xlnx_16x19_2clk_flist.txt
new file mode 100644
index 000000000..5e1a6ed35
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk_flist.txt
@@ -0,0 +1,8 @@
+# Output products list for <fifo_xlnx_16x19_2clk>
+fifo_xlnx_16x19_2clk.ngc
+fifo_xlnx_16x19_2clk.v
+fifo_xlnx_16x19_2clk.veo
+fifo_xlnx_16x19_2clk.xco
+fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+fifo_xlnx_16x19_2clk_flist.txt
+fifo_xlnx_16x19_2clk_xmdf.tcl
diff --git a/coregen/fifo_xlnx_16x19_2clk_readme.txt b/coregen/fifo_xlnx_16x19_2clk_readme.txt
new file mode 100644
index 000000000..1b5976555
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk_readme.txt
@@ -0,0 +1,39 @@
+The following files were generated for 'fifo_xlnx_16x19_2clk' in directory
+/home/matt/gnuradio.git/usrp2/fpga/coregen/:
+
+fifo_xlnx_16x19_2clk.ngc:
+ Binary Xilinx implementation netlist file containing the information
+ required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_16x19_2clk.v:
+ Verilog wrapper file provided to support functional simulation.
+ This file contains simulation model customization data that is
+ passed to a parameterized simulation model for the core.
+
+fifo_xlnx_16x19_2clk.veo:
+ VEO template file containing code that can be used as a model for
+ instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_16x19_2clk.xco:
+ CORE Generator input file containing the parameters used to
+ regenerate a core.
+
+fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
+ Please see the core data sheet.
+
+fifo_xlnx_16x19_2clk_flist.txt:
+ Text file listing all of the output files produced when a customized
+ core was generated in the CORE Generator.
+
+fifo_xlnx_16x19_2clk_readme.txt:
+ Text file indicating the files generated and how they are used.
+
+fifo_xlnx_16x19_2clk_xmdf.tcl:
+ ISE Project Navigator interface file. ISE uses this file to determine
+ how the files output by CORE Generator for the core can be integrated
+ into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl b/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
new file mode 100644
index 000000000..8d633e9c2
--- /dev/null
+++ b/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_16x19_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_16x19_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x19_2clk
+}
+# ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x19_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 10:48:59 +0000