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author | Sugandha Gupta <sugandha.gupta@ettus.com> | 2018-06-05 13:48:07 -0700 |
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committer | Martin Braun <martin.braun@ettus.com> | 2018-06-15 16:37:03 -0500 |
commit | 67b5827faecd3dc3d9977dff7366b8ea2ab4c87a (patch) | |
tree | 8d4d6b3645cd4b1aa72e26b4be4b5e81d5c45bfa /.gitignore | |
parent | f9101d7cc7552755d597982eeccecabe88b8a022 (diff) | |
download | uhd-67b5827faecd3dc3d9977dff7366b8ea2ab4c87a.tar.gz uhd-67b5827faecd3dc3d9977dff7366b8ea2ab4c87a.tar.bz2 uhd-67b5827faecd3dc3d9977dff7366b8ea2ab4c87a.zip |
ad9361: Add API to set 1R1T/2R2T timing modes
LVDS interface can support both timing modes 1R1T/2R2T
The API sets the required bit in catalina registers.
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