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| author | michael-west <michael.west@ettus.com> | 2021-07-26 13:48:34 -0700 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-08-10 15:19:32 -0500 |
| commit | 1fecf446e0358aa2b6a2d1f73a0daeac516435a0 (patch) | |
| tree | 26570f0483adc70fc3e4f521284943dee9f311b6 /.ci | |
| parent | 807987361f2ba3df3562c24f579d02010ca47172 (diff) | |
| download | uhd-1fecf446e0358aa2b6a2d1f73a0daeac516435a0.tar.gz uhd-1fecf446e0358aa2b6a2d1f73a0daeac516435a0.tar.bz2 uhd-1fecf446e0358aa2b6a2d1f73a0daeac516435a0.zip | |
fpga: Fix sc16 to sc12 converter
Re-wrote converter to remove clock cycle delay on i_tready when handling
residual output and fixed improper handling of tlast during residual
data processing. Resolves some USB overflow issues when using sc12 data
type on B200 devices.
Signed-off-by: michael-west <michael.west@ettus.com>
Diffstat (limited to '.ci')
0 files changed, 0 insertions, 0 deletions