interface hla
hla_layout stlink
hla_device_desc "ST-LINK"
hla_vid_pid 0x0483 0x374b

transport select hla_swd

if [catch {transport select}] {
    echo "Error: unable to select a session transport. Can't continue."
    shutdown
}

proc swj_newdap {chip tag args} {
    if [using_hla] {
        eval hla newtap $chip $tag $args
    } elseif [using_jtag] {
        eval jtag newtap $chip $tag $args
    } elseif [using_swd] {
        eval swd newdap $chip $tag $args
    }
}
proc mrw {reg} {
    set value ""
    mem2array value 32 $reg 1
    return $value(0)
}

add_usage_text mrw "address"
add_help_text mrw "Returns value of word in memory."

proc mrb {reg} {
    set value ""
    mem2array value 8 $reg 1
    return $value(0)
}

add_usage_text mrb "address"
add_help_text mrb "Returns value of byte in memory."

proc mmw {reg setbits clearbits} {
    set old [mrw $reg]
    set new [expr ($old & ~$clearbits) | $setbits]
    mww $reg $new
}

add_usage_text mmw "address setbits clearbits"
add_help_text mmw "Modify word in memory. new_val = (old_val & ~clearbits) | setbits;"

if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
} else {
    set _CHIPNAME stm32h7x
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 64kB
if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
} else {
    set _WORKAREASIZE 0x10000
}

#jtag scan chain
if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
} else {
    if { [using_jtag] } {
        set _CPUTAPID 0x6ba00477
    } {
        set _CPUTAPID 0x6ba02477
    }
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

if {[using_jtag]} {
    swj_newdap $_CHIPNAME bs -irlen 5
}

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME

# Clock after reset is HSI at 64 MHz, no need of PLL
adapter_khz 1800

adapter_nsrst_delay 100
if {[using_jtag]} {
 jtag_ntrst_delay 100
}

# use hardware reset, connect under reset
reset_config srst_only srst_nogate

if {![using_hla]} {
   # if srst is not fitted use SYSRESETREQ to
   # perform a soft reset
   cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event examine-end {
    # Enable D3 and D1 DBG clocks
    # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
    mmw 0x5C001004 0x00600000 0

    # Enable debug during low power modes (uses more power)
    # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
    mmw 0x5C001004 0x00000187 0

    # Stop watchdog counters during halt
    # DBGMCU_APB3FZ1 |= WWDG1
    mmw 0x5C001034 0x00000040 0
    # DBGMCU_APB4FZ1 |= WDGLSD1
    mmw 0x5C001054 0x00040000 0
}

$_TARGETNAME configure -event trace-config {
    # Set TRACECLKEN; TRACE_MODE is set to async; when using sync
    # change this value accordingly to configure trace pins
    # assignment
    mmw 0x5C001004 0x00100000 0
}

$_TARGETNAME configure -event reset-init {
    # Clock after reset is HSI at 64 MHz, no need of PLL
    adapter_khz 4000
}

# STM32H7xxxI 2Mo have a dual bank flash.
# Add the second flash bank.
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32h7x 0x08100000 0 0 0 $_TARGETNAME

reset_config srst_only