Picardy 2020 ============ A reinterpretation of the [Picardy 2m SSB transceiver](http://f6feo.homebuilder.free.fr/transceiver_PICARDY.html) by F6FEO combined with the [Anglian 3L transverter](http://www.g4ddk.com/Products.html). Additional inspirations: uBitx, the KN-Q7, LimeRFE and EI9GQ's "Building a Transceiver" book. Many thanks to all the designers behind these projects. The hardware design is licenced under the "CERN Open Hardware Licence Version 2 - Permissive", see *cern_ohl_p_v2.txt*. The firmware is MIT-licenced. * Designed in KiCad * Meant to be used with a microwave transverter * But also stand-alone 144MHz * Offer plug-in band-filters for other HF bands * Using a STM32F103C8T6 controller * Programmed in [Rust](https://rust-lang.org/) * Si5351 clock source (generates clocks) * An LCD display * Discarded ideas * Include a Lars Widenius GPSDO originally published on [eevblog](https://www.eevblog.com/forum/projects/lars-diy-gpsdo-with-arduino-and-1ns-resolution-tic/?all) * Offer a 10MHz output refclk for a transverter * Instead, have a 25MHz ref input, and use a LeoBodnar reference * Use the Si5351 to generate the VHF LO at 116 MHz * It wasn't clean enough, so a separate [XTAL LO board](./lo_board/) was designed * With a 114.286 MHz crystal, we get a first IF of 29714 kHz *First QSO done with this transceiver and MMRF1021 amplifier on 2020-12-07* On RX, an [LNA4ALL](http://lna4all.blogspot.com/) LNA was used. On TX, 2x SPF5189Z, a bandpass filter to remove the LO, and the [MMRF1021](http://git.mpb.li/git/mmrf1021-pa/about/) amplifier were used, giving about 200mW output power on the very first trial. Open questions ============== * CW * Does the trick with the DC bias to leak the LO work ? * Not tested, but plan B done (J306) * Use an additional PWM output for plan B? * Put sidetone volume setting before RV303? * Hook up to LM375 BYPASS? Issues ====== * Coupling between VHF filter coils was way too large * Fixed, replacement of coupling caps. * SEQ0 is used in inverted-logic in baseband, and noninverted for power relay * Due to inconsistent naming * Ugly fix on K603 side, use SEQ0n, SEQ1, SEQ2 * G6K-2F-RF all have the Y footprint, not the equidistant one. * And they have additional GND flaps too, which are not in the Kicad footprint library * Can be kludged-in * 5V jumper is less useful as hoped * Intention: disable VHF stuff * Unintended effect: removes LCD backlight * Are 10uH for L311 and L305 ok too? * C319 and C326 are redundant * BC856W wrong footprint * R327 upsets DC offset of audio amp, capacitive decoupling needed * 2m filters from LimeRFE use values I don't stash * 20pF done with 2x 10pF * SW: ADC input for buttons looks messed up... * Connect 3V3 LDO to 12V directly * Add 2.2uF caps near consumers * Replace C535, C536 * Replace C343, C315 * Next to R508 * Next to R305 * Parallel to C331 * Parallel to C607 * Next to R306 * Next to R504 * Next to R328 * Next to R515 * I still have spurious next to transmit frequency, spaced 200kHz because of the DCDC converter * Measure 8V current! PCB Assembly Plan ================= 1. DCDC converter for 8V and LDOs * Check output voltages * Check drop under load 2. STM32F103C8T6 * Programming * Sidetone low-pass * Probably need to do a UI proto already 3. Si5153 * Check I2C works 4. 8V and 5V relay * Check switching with microcontroller and validate resistors 5. Baseband * Crystal filter shape * RX and TX filter shape * Receive path: IF mixer, crystal filter relay, IF AGC, BFO mixer, AGC measure, AF amp, SPKR * Verify LO levels into SA602A: at least 200mVpp * Transmit path: Mic amp 6. Anglian * LO filter shape * LO amp. Mixer needs +7dBm * All passives * Verify correct voltages for amplifiers * Verify PIN currents (Between 20mA and 60mA, below 0.8V) * Verify filter shapes * IF amplifiers, both RX and TX * VHF amplifiers * VHF bandpass filter * Mixer 7. External switching relay Tuning ====== IF gain (R307) Define if we need C361, C360 Ensure LO1 and BFO voltage level at TP301 TP302 Additional remarks ================== Very good [explanations](https://groups.io/g/BITX20/topic/si5351a_facts_and_myths/5430607) about DDS vs DPLL from Hans Summers Si5153 test before PCB fab: * It seems the desired frequency plan can be achieved: * clk0: LO1 = 28 - 4.9152 + VFO, i.e. from 23 to 25 * clk1: VHF-LO = 144 + 28 and 144 - 28, i.e. 116 MHz * clk2: BFO = 4.91521 * See `freqplan.py` * If not, generate LO1 and BFO with Si5153, and connect an external LO to the VHF LO u.FL * No 116MHz crystals on mouser, but 114.285MHz are available, HF bandpass filters recalculated. * Other option is using another configurable reference