From b2b6ac9eea2eb5066942237bfced3f7f8b48c43c Mon Sep 17 00:00:00 2001 From: "Matthias P. Braendli" Date: Mon, 29 Mar 2021 22:46:08 +0200 Subject: Work on eval-clock-cw-tx sequencing --- sw/eval-clock-cw-tx/src/state.rs | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'sw/eval-clock-cw-tx/src/state.rs') diff --git a/sw/eval-clock-cw-tx/src/state.rs b/sw/eval-clock-cw-tx/src/state.rs index b3b0b7b..a5891c5 100644 --- a/sw/eval-clock-cw-tx/src/state.rs +++ b/sw/eval-clock-cw-tx/src/state.rs @@ -66,13 +66,23 @@ impl State { } } - pub fn vfo(&self) -> u32 { + pub fn vfo_display(&self) -> u32 { match self.vfo_sel { VFOSelection::A => self.vfo_a, VFOSelection::B => self.vfo_b, } } + pub fn vfo_siclock(&self) -> u32 { + match self.sequence_state { + SequenceState::Rx => 0, + _ => match self.vfo_sel { + VFOSelection::A => self.vfo_a, + VFOSelection::B => self.vfo_b, + } + } + } + pub fn vfo_incr(&self) -> i32 { match self.tune_speed { TuneSpeed::Slow => 10, -- cgit v1.2.3