From 5d1cff57f9f5acd740a8b5f8c941beefdcc00176 Mon Sep 17 00:00:00 2001 From: "Matthias P. Braendli" Date: Sun, 28 Jun 2020 16:42:21 +0200 Subject: sw: configure si5351 --- .../hd44780-driver/examples/stm32f30x/openocd.gdb | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 sw/deps/hd44780-driver/examples/stm32f30x/openocd.gdb (limited to 'sw/deps/hd44780-driver/examples/stm32f30x/openocd.gdb') diff --git a/sw/deps/hd44780-driver/examples/stm32f30x/openocd.gdb b/sw/deps/hd44780-driver/examples/stm32f30x/openocd.gdb new file mode 100644 index 0000000..a7fd5d1 --- /dev/null +++ b/sw/deps/hd44780-driver/examples/stm32f30x/openocd.gdb @@ -0,0 +1,32 @@ +target extended-remote :3333 + +# print demangled symbols +set print asm-demangle on + +# detect unhandled exceptions, hard faults and panics +break DefaultHandler +break UserHardFault +break rust_begin_unwind + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +monitor arm semihosting enable + +# # send captured ITM to the file itm.fifo +# # (the microcontroller SWO pin must be connected to the programmer SWO pin) +# # 8000000 must match the core clock frequency +# monitor tpiu config internal itm.txt uart off 8000000 + +# # OR: make the microcontroller SWO pin output compatible with UART (8N1) +# # 8000000 must match the core clock frequency +# # 2000000 is the frequency of the SWO pin +# monitor tpiu config external uart off 8000000 2000000 + +# # enable ITM port 0 +# monitor itm port 0 on + +load + +# start the process but immediately halt the processor +stepi -- cgit v1.2.3