diff options
Diffstat (limited to 'sw/picardy/src/si_clock.rs')
| -rw-r--r-- | sw/picardy/src/si_clock.rs | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/sw/picardy/src/si_clock.rs b/sw/picardy/src/si_clock.rs index b304461..8ebf702 100644 --- a/sw/picardy/src/si_clock.rs +++ b/sw/picardy/src/si_clock.rs @@ -101,18 +101,9 @@ impl<I2C, E> SiClock<I2C> siclock.init(si5351::CrystalLoad::_10).unwrap(); // See freqplan.py for Si5351 frequency plan - // CLK1 = 116MHz + // CLK1 unused siclock.setup_pll_int(si5351::PLL::A, 32).unwrap(); - { - let clk1 = 116_000_000; - let (a, b, c) = clock_settings_for_pll(clk1, PLL_A_MULT * REF_CLOCK); - siclock.setup_multisynth(si5351::Multisynth::MS1, a, b, c, si5351::OutputDivider::Div1).unwrap(); - siclock.select_clock_pll(si5351::ClockOutput::Clk1, si5351::PLL::A); - siclock.set_clock_enabled(si5351::ClockOutput::Clk1, true); - siclock.flush_clock_control(si5351::ClockOutput::Clk1).unwrap(); - } - set_bfo(&mut siclock, bfo).unwrap(); siclock.reset_pll(si5351::PLL::A).unwrap(); |