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-rw-r--r--sw/eval-clock-cw-tx/src/main.rs5
1 files changed, 5 insertions, 0 deletions
diff --git a/sw/eval-clock-cw-tx/src/main.rs b/sw/eval-clock-cw-tx/src/main.rs
index 52193b4..c303416 100644
--- a/sw/eval-clock-cw-tx/src/main.rs
+++ b/sw/eval-clock-cw-tx/src/main.rs
@@ -273,6 +273,11 @@ fn main() -> ! {
}
},
Mode::WSPR => {
+ if let Some(f) = usb.take_frequency() {
+ shared.state.set_vfo(f);
+ update_siclock_required = true;
+ }
+
if shared.state.wspr_freq_offset_updated {
update_siclock_required = true;
}