aboutsummaryrefslogtreecommitdiffstats
path: root/README.md
diff options
context:
space:
mode:
authorMatthias P. Braendli <matthias.braendli@mpb.li>2020-07-08 11:28:13 +0200
committerMatthias P. Braendli <matthias.braendli@mpb.li>2020-07-08 11:28:13 +0200
commitde8199d54df4fadc2dff9be17535a7b3796ef56c (patch)
tree815859695a45a99f1a7a5f6ccd9ac276b42b03c3 /README.md
parent5e9e5facc4fde8f8948588bb3a068618c91bdb85 (diff)
downloadpicardy-de8199d54df4fadc2dff9be17535a7b3796ef56c.tar.gz
picardy-de8199d54df4fadc2dff9be17535a7b3796ef56c.tar.bz2
picardy-de8199d54df4fadc2dff9be17535a7b3796ef56c.zip
Clarify licences
Diffstat (limited to 'README.md')
-rw-r--r--README.md14
1 files changed, 10 insertions, 4 deletions
diff --git a/README.md b/README.md
index 6e71480..6e9a6b6 100644
--- a/README.md
+++ b/README.md
@@ -3,10 +3,16 @@ Picardy 2020
A reinterpretation of the [Picardy 2m SSB transceiver](http://f6feo.homebuilder.free.fr/transceiver_PICARDY.html) by F6FEO
combined with the [Anglian 3L transverter](http://www.g4ddk.com/Products.html).
+Additional inspirations: uBitx, the KN-Q7, LimeRFE and EI9GQ's "Building a Transceiver" book. Many thanks to all the
+designers behind these projects.
+
+The hardware design is licenced under the "CERN Open Hardware Licence Version 2 - Permissive", see *cern_ohl_p_v2.txt*.
+The firmware is MIT-licenced.
* Designed in KiCad
* Meant to be used with a microwave transverter
* But also stand-alone 28MHz and 144MHz (The IF bands)
+ * Offer plug-in band-filters for other HF bands
* Using a STM32F103C8T6 controller
* Si5351 clock source (generates 3 clocks)
* An LCD display
@@ -15,10 +21,8 @@ combined with the [Anglian 3L transverter](http://www.g4ddk.com/Products.html).
* Offer a 10MHz output refclk for a transverter
* Instead, have a 25MHz ref input, and use a LeoBodnar reference
-* Very good [explanations](https://groups.io/g/BITX20/topic/si5351a_facts_and_myths/5430607) about DDS vs DPLL from Hans Summers
-
-TODO before ordering the PCB
-============================
+Open questions
+==============
* CW
* Does the trick with the DC bias to leak the LO work ?
@@ -70,6 +74,8 @@ PCB Assembly Plan
Additional remarks
==================
+* Very good [explanations](https://groups.io/g/BITX20/topic/si5351a_facts_and_myths/5430607) about DDS vs DPLL from Hans Summers
+
* Si5153 test before PCB fab:
* It seems the desired frequency plan can be achieved:
* clk0: LO1 = 28 - 4.9152 + VFO, i.e. from 23 to 25