From bb6be8d6bf84071ad04247163932fecff500367e Mon Sep 17 00:00:00 2001
From: Hirosh Dabui <hirosh@dabui.de>
Date: Tue, 11 Feb 2020 20:15:16 +0100
Subject: ported fpga fun music examples to iceFun. iceFun has built-in
 speakers.

---
 music/fpga4fun/simple_beep/top.v | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 music/fpga4fun/simple_beep/top.v

(limited to 'music/fpga4fun/simple_beep/top.v')

diff --git a/music/fpga4fun/simple_beep/top.v b/music/fpga4fun/simple_beep/top.v
new file mode 100644
index 0000000..069e4d1
--- /dev/null
+++ b/music/fpga4fun/simple_beep/top.v
@@ -0,0 +1,35 @@
+/*
+* (c) https://www.fpga4fun.com
+*
+  * ported to iceFun FPGA by Hirosh Dabui <hirosh@dabui.de>
+  */
+module top (
+ input clk12MHz,
+ output spkp,
+ output spkm
+);
+
+wire clk;
+assign spkp = speaker;
+assign spkm = ~speaker;
+// 25 MHz PLL
+SB_PLL40_CORE #(
+ .FEEDBACK_PATH("SIMPLE"),
+ .DIVR(4'b0000),         // DIVR =  0
+ .DIVF(7'b1000010),      // DIVF = 66
+ .DIVQ(3'b101),          // DIVQ =  5
+ .FILTER_RANGE(3'b001)   // FILTER_RANGE = 1
+) uut (
+ .LOCK(locked),
+ .RESETB(1'b1),
+ .BYPASS(1'b0),
+ .REFERENCECLK(clk12MHz),
+ .PLLOUTCORE(clk)
+);
+
+reg [15:0] counter;
+always @(posedge clk) counter <= counter+1;
+
+// and use the most significant bit (MSB) of the counter to drive the speaker
+ assign speaker = counter[15];
+endmodule
-- 
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