14 files changed, 3158 insertions, 0 deletions

diff --git a/lib/Makefile.am b/lib/Makefile.am
new file mode 100644
index 0000000..d2bb342
--- /dev/null
+++ b/lib/Makefile.am
@@ -0,0 +1,19 @@
+# Copyright (C) 2009 Her Majesty the Queen in Right of Canada (Communications
+# Research Center Canada)
+
+# This file is part of CRC-DabMux.
+# 
+# CRC-DabMux is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as
+# published by the Free Software Foundation, either version 3 of the
+# License, or (at your option) any later version.
+# 
+# CRC-DabMux is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with CRC-DabMux.  If not, see <http://www.gnu.org/licenses/>.
+
+SUBDIRS =farsync
diff --git a/lib/Makefile.in b/lib/Makefile.in
new file mode 100644
index 0000000..7491c8b
--- /dev/null
+++ b/lib/Makefile.in
@@ -0,0 +1,558 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009  Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# Copyright (C) 2009 Her Majesty the Queen in Right of Canada (Communications
+# Research Center Canada)
+
+# This file is part of CRC-DabMux.
+# 
+# CRC-DabMux is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as
+# published by the Free Software Foundation, either version 3 of the
+# License, or (at your option) any later version.
+# 
+# CRC-DabMux is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with CRC-DabMux.  If not, see <http://www.gnu.org/licenses/>.
+VPATH = @srcdir@
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+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
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diff --git a/lib/farsync/Makefile.am b/lib/farsync/Makefile.am
new file mode 100644
index 0000000..858c150
--- /dev/null
+++ b/lib/farsync/Makefile.am
@@ -0,0 +1 @@
+EXTRA_DIST  =linux windows
diff --git a/lib/farsync/Makefile.in b/lib/farsync/Makefile.in
new file mode 100644
index 0000000..435618f
--- /dev/null
+++ b/lib/farsync/Makefile.in
@@ -0,0 +1,338 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009  Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
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+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
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+all: all-am
+
+.SUFFIXES:
+$(srcdir)/Makefile.in:  $(srcdir)/Makefile.am  $(am__configure_deps)
+	@for dep in $?; do \
+	  case '$(am__configure_deps)' in \
+	    *$$dep*) \
+	      ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+	        && { if test -f $@; then exit 0; else break; fi; }; \
+	      exit 1;; \
+	  esac; \
+	done; \
+	echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu lib/farsync/Makefile'; \
+	$(am__cd) $(top_srcdir) && \
+	  $(AUTOMAKE) --gnu lib/farsync/Makefile
+.PRECIOUS: Makefile
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+	@case '$?' in \
+	  *config.status*) \
+	    cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
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+	      cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+	      find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+	    fi; \
+	    cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+	  else \
+	    test -f "$(distdir)/$$file" \
+	    || cp -p $$d/$$file "$(distdir)/$$file" \
+	    || exit 1; \
+	  fi; \
+	done
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+	install install-am install-data install-data-am install-dvi \
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+	install-pdf install-pdf-am install-ps install-ps-am \
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+	maintainer-clean maintainer-clean-generic mostlyclean \
+	mostlyclean-generic pdf pdf-am ps ps-am uninstall uninstall-am
+
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/lib/farsync/linux/CVS/Entries b/lib/farsync/linux/CVS/Entries
new file mode 100644
index 0000000..1c2d89c
--- /dev/null
+++ b/lib/farsync/linux/CVS/Entries
@@ -0,0 +1,2 @@
+/farsync.h/1.1.1.1/Wed Sep  9 22:14:15 2009//
+D
diff --git a/lib/farsync/linux/CVS/Repository b/lib/farsync/linux/CVS/Repository
new file mode 100644
index 0000000..981d916
--- /dev/null
+++ b/lib/farsync/linux/CVS/Repository
@@ -0,0 +1 @@
+crc-dabmux/lib/farsync/linux
diff --git a/lib/farsync/linux/CVS/Root b/lib/farsync/linux/CVS/Root
new file mode 100644
index 0000000..9e5f945
--- /dev/null
+++ b/lib/farsync/linux/CVS/Root
@@ -0,0 +1 @@
+:pserver:pascal@mmlab.dgbt.crc.ca:/home/cvsroot
diff --git a/lib/farsync/linux/farsync.h b/lib/farsync/linux/farsync.h
new file mode 100644
index 0000000..adc4e3a
--- /dev/null
+++ b/lib/farsync/linux/farsync.h
@@ -0,0 +1,507 @@
+/*
+ *      FarSync X21 driver for Linux
+ *
+ *      Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
+ *
+ *      Copyright (C) 2001-2004 FarSite Communications Ltd.
+ *      www.farsite.co.uk
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ *      Author: R.J.Dunlop      <bob.dunlop@farsite.co.uk>
+ *
+ *      For the most part this file only contains structures and information
+ *      that is visible to applications outside the driver. Shared memory
+ *      layout etc is internal to the driver and described within farsync.c.
+ *      Overlap exists in that the values used for some fields within the
+ *      ioctl interface extend into the cards firmware interface so values in
+ *      this file may not be changed arbitrarily.
+ */
+
+#define FST_NAME                "fst"           /* In debug/info etc */
+#define FST_NDEV_NAME           "sync"          /* For net interface */
+#define FST_DEV_NAME            "farsync"       /* For misc interfaces */
+
+/*      User version number
+ *
+ *      This version number is incremented with each official release of the
+ *      package and is a simplified number for normal user reference.
+ *      Individual files are tracked by the version control system and may
+ *      have individual versions (or IDs) that move much faster than the
+ *      the release version as individual updates are tracked.
+ */
+#define FST_USER_VERSION        "1.06"
+#define FST_PATCH_LEVEL         "02"
+#define FST_PLATFORM            "ia32"
+#define FST_ADDITIONAL          "-T1"
+
+#define FST_INCLUDES_CHAR
+
+/*      Ioctl call command values
+ *
+ *      The first three private ioctls are used by the sync-PPP module,
+ *      allowing a little room for expansion we start our numbering at 10.
+ */
+#define FSTWRITE        (SIOCDEVPRIVATE+4)
+#define FSTCPURESET     (SIOCDEVPRIVATE+5)
+#define FSTCPURELEASE   (SIOCDEVPRIVATE+6)
+#define FSTGETCONF      (SIOCDEVPRIVATE+7)
+#define FSTSETCONF      (SIOCDEVPRIVATE+8)
+#define FSTSNOTIFY      (SIOCDEVPRIVATE+9)
+#define FSTGSTATE       (SIOCDEVPRIVATE+10)
+#define FSTSYSREQ       (SIOCDEVPRIVATE+11)
+#define FSTGETSHELL     (SIOCDEVPRIVATE+12)
+#define FSTSETMON       (SIOCDEVPRIVATE+13)
+#define FSTSETPORT      (SIOCDEVPRIVATE+14)
+
+
+/*      FSTWRITE
+ *
+ *      Used to write a block of data (firmware etc) before the card is running
+ */
+struct fstioc_write {
+        unsigned int  size;
+        unsigned int  offset;
+        unsigned char data[0];
+};
+
+
+/*      FSTCPURESET and FSTCPURELEASE
+ *
+ *      These take no additional data.
+ *      FSTCPURESET forces the cards CPU into a reset state and holds it there.
+ *      FSTCPURELEASE releases the CPU from this reset state allowing it to run,
+ *      the reset vector should be setup before this ioctl is run.
+ */
+
+/*      FSTGETCONF and FSTSETCONF
+ *
+ *      Get and set a card/ports configuration.
+ *      In order to allow selective setting of items and for the kernel to
+ *      indicate a partial status response the first field "valid" is a bitmask
+ *      indicating which other fields in the structure are valid.
+ *      Many of the field names in this structure match those used in the
+ *      firmware shared memory configuration interface and come originally from
+ *      the NT header file Smc.h
+ *
+ *      When used with FSTGETCONF this structure should be zeroed before use.
+ *      This is to allow for possible future expansion when some of the fields
+ *      might be used to indicate a different (expanded) structure.
+ */
+struct fstioc_info {
+        unsigned int   valid;           /* Bits of structure that are valid */
+        unsigned int   nports;          /* Number of serial ports */
+        unsigned int   type;            /* Type index of card */
+        unsigned int   state;           /* State of card */
+        unsigned int   index;           /* Index of port ioctl was issued on */
+        unsigned int   smcFirmwareVersion;
+        unsigned long  kernelVersion;   /* What Kernel version we are working with */
+        unsigned short lineInterface;   /* Physical interface type */
+        unsigned char  proto;           /* Line protocol */
+        unsigned char  internalClock;   /* 1 => internal clock, 0 => external */
+        unsigned int   lineSpeed;       /* Speed in bps */
+        unsigned int   estLineSpeed;    /* Estimated speed in bps */
+        unsigned int   v24IpSts;        /* V.24 control input status */
+        unsigned int   v24OpSts;        /* V.24 control output status */
+        unsigned short clockStatus;     /* lsb: 0=> present, 1=> absent */
+        unsigned short cableStatus;     /* lsb: 0=> present, 1=> absent */
+        unsigned short cardMode;        /* lsb: LED id mode */
+        unsigned short debug;           /* Debug flags */
+        unsigned char  transparentMode; /* Not used always 0 */
+        unsigned char  invertClock;     /* Invert clock feature for syncing */
+        unsigned char  asyncAbility ;   /* The ability to do async */
+        unsigned char  synthAbility;    /* The ability to syth a clock */
+        unsigned char  startingSlot;    /* Time slot to use for start of tx */
+        unsigned char  clockSource;     /* External or internal */
+        unsigned char  framing;         /* E1, T1 or J1 */
+        unsigned char  structure;       /* unframed, double, crc4, f4, f12, */
+                                        /* f24 f72 */
+        unsigned char  interface;       /* rj48c or bnc */
+        unsigned char  coding;          /* hdb3 b8zs */
+        unsigned char  lineBuildOut;    /* 0, -7.5, -15, -22 */
+        unsigned char  equalizer;       /* short or lon haul settings */
+        unsigned char  loopMode;        /* various loopbacks */
+        unsigned char  range;           /* cable lengths */
+        unsigned char  txBufferMode;    /* tx elastic buffer depth */
+        unsigned char  rxBufferMode;    /* rx elastic buffer depth */
+        unsigned char  losThreshold;    /* Attenuation on LOS signal */
+        unsigned char  idleCode;        /* Value to send as idle timeslot */
+        unsigned int   receiveBufferDelay; /* delay thro rx buffer timeslots */
+        unsigned int   framingErrorCount; /* framing errors */
+        unsigned int   codeViolationCount; /* code violations */
+        unsigned int   crcErrorCount;   /* CRC errors */
+        int            lineAttenuation; /* in dB*/
+        unsigned short lossOfSignal;
+        unsigned short receiveRemoteAlarm;
+        unsigned short alarmIndicationSignal;
+        unsigned short _reserved[64];
+        unsigned char  ignoreCarrier;  /* If set transmit regardless of carrier state */
+        unsigned char  numTxBuffers;   /* No of tx buffers in card window */
+        unsigned char  numRxBuffers;   /* No of rx buffers in card window */
+        unsigned int   txBufferSize;   /* Size of tx buffers in card window */
+        unsigned int   rxBufferSize;   /* Size of rx buffers in card window */
+        unsigned char  terminalType;  /* Additional hdsl */
+        unsigned char  annexType;
+        unsigned char  encap;
+        unsigned char  testMode;
+        unsigned char  backoff;
+        unsigned char  bLineProbingEnable;
+        unsigned char  snrth;
+        unsigned char  lpath;
+        unsigned short vpi;
+        unsigned short vci;
+        unsigned char  activationStatus;
+        unsigned char  noCommonModeStatus;
+        unsigned char  transceiverStatus1;
+        unsigned char  transceiverStatus2;
+        unsigned char  lineLoss;
+        char           signalQuality;
+        unsigned char  nearEndBlockErrorCount;
+        char           signalToNoiseRatio;
+        unsigned char  erroredSecondCount;
+        unsigned char  severelyErroredSecondCount;
+        unsigned char  lossOfSyncWordSecondCount;
+        unsigned char  unavailableSecondCount;
+        char           frequencyDeviation;
+        char           negotiatedPowerBackOff;
+        unsigned char  negotiatedPSD;
+        unsigned char  negotiatedBChannels;
+        unsigned char  negotiatedZBits;
+        unsigned short negotiatedSyncWord;
+        unsigned char  negotiatedStuffBits;
+        unsigned char  chipVersion;
+        unsigned char  firmwareVersion;
+        unsigned char  romVersion;
+        unsigned short atmTxCellCount;
+        unsigned short atmRxCellCount;
+        unsigned short atmHecErrorCount;
+        unsigned int   atmCellsDropped;
+        unsigned char  transmitMSBFirst;
+        unsigned char  receiveMSBFirst;
+};
+
+/*      FSTGSTATE
+ *
+ *      Used to query why a state change message has been issued by the driver
+ *      It could be because there was a change in line states or that the txq
+ *      has reached an empty state
+ */
+struct fstioc_status {
+  int carrier_state;
+  int txq_length;
+};
+
+/*      FSTSYSREQ
+ *
+ *      Used to provide a simple transparent command/repsonse interface between
+ *      an application and the firmware running on the card
+ */
+struct fstioc_req {
+  unsigned short msg_type;
+  unsigned short msg_len;
+  unsigned short ret_code;
+  unsigned short i_reg_idx;
+  unsigned short value;
+  unsigned char u_msg[16];
+  unsigned char u_msg_reserved[16];
+  unsigned char u_reserved[4];
+};
+
+
+#define MSG_FIFO_EEPROM_RD 0x769b
+#define MSG_FIFO_EEPROM_WR 0xcd4a
+#define RSP_FIFO_SUCCESS   0x0000
+#define RSP_FIFO_FAILURE   0x0001
+
+
+/*      FSTSETMON
+ *
+ *      Used to provide a simple monitoring data 
+ */
+#define FSTIOC_MON_VERSION 0
+#define FST_MON_RX         0
+#define FST_MON_TX         1
+
+struct fstioc_mon {
+  unsigned char version;
+  unsigned char tx_rx_ind;
+  unsigned int  sequence;
+  unsigned long timestamp;
+  unsigned int  length;
+};
+
+/*      FSTSETPORT
+ *
+ *      Used to provide a DSL port control
+ */
+#define FST_DSL_PORT_NORMAL         0
+#define FST_DSL_PORT_ACTIVE         1
+
+/* "valid" bitmask */
+#define FSTVAL_NONE     0x00000000      /* Nothing valid (firmware not running).
+                                         * Slight misnomer. In fact nports,
+                                         * type, state and index will be set
+                                         * based on hardware detected.
+                                         */
+#define FSTVAL_OMODEM   0x0000001F      /* First 5 bits correspond to the
+                                         * output status bits defined for
+                                         * v24OpSts
+                                         */
+#define FSTVAL_SPEED    0x00000020      /* internalClock, lineSpeed, clockStatus
+                                         */
+#define FSTVAL_CABLE    0x00000040      /* lineInterface, cableStatus */
+#define FSTVAL_IMODEM   0x00000080      /* v24IpSts */
+#define FSTVAL_CARD     0x00000100      /* nports, type, state, index,
+                                         * smcFirmwareVersion
+                                         */
+#define FSTVAL_PROTO    0x00000200      /* proto */
+#define FSTVAL_MODE     0x00000400      /* cardMode */
+#define FSTVAL_PHASE    0x00000800      /* Clock phase */
+#define FSTVAL_TE1      0x00001000      /* T1E1 Configuration */
+#define FSTVAL_BUFFERS  0x00002000      /* Tx and Rx buffer settings */
+#define FSTVAL_DSL_S1   0x00004000      /* DSL-S1 Configuration */
+#define FSTVAL_T4E      0x00008000      /* T4E Mk II Configuration */
+#define FSTVAL_DEBUG    0x80000000      /* debug */
+#define FSTVAL_ALL      0x0000FFFF      /* Note: does not include DEBUG flag */
+
+/* "type" */
+#define FST_TYPE_NONE   0               /* Probably should never happen */
+#define FST_TYPE_T2P    1               /* T2P X21 2 port card */
+#define FST_TYPE_T4P    2               /* T4P X21 4 port card */
+#define FST_TYPE_T1U    3               /* T1U X21 1 port card */
+#define FST_TYPE_T2U    4               /* T2U X21 2 port card */
+#define FST_TYPE_T4U    5               /* T4U X21 4 port card */
+#define FST_TYPE_TE1    6               /* T1E1 X21 1 port card */
+#define FST_TYPE_DSL_S1 7               /* DSL-S1 card */
+#define FST_TYPE_T4E    8               /* T4E Mk II */
+
+/* "family" */
+#define FST_FAMILY_TXP  0               /* T2P or T4P */
+#define FST_FAMILY_TXU  1               /* T1U or T2U or T4U */
+
+/* "state" */
+#define FST_UNINIT      0               /* Raw uninitialised state following
+                                         * system startup */
+#define FST_RESET       1               /* Processor held in reset state */
+#define FST_DOWNLOAD    2               /* Card being downloaded */
+#define FST_STARTING    3               /* Released following download */
+#define FST_RUNNING     4               /* Processor running */
+#define FST_BADVERSION  5               /* Bad shared memory version detected */
+#define FST_HALTED      6               /* Processor flagged a halt */
+#define FST_IFAILED     7               /* Firmware issued initialisation failed
+                                         * interrupt
+                                         */
+/* "lineInterface" */
+#define V24             1
+#define X21             2
+#define V35             3
+#define X21D            4
+#define NOCABLE         5
+#define RS530_449       6
+#define T1              7
+#define E1              8
+#define J1              9
+#define SHDSL           10
+
+/* "proto" */
+#define FST_HDLC        1               /* Cisco compatible HDLC */
+#define FST_PPP         2               /* Sync PPP */
+#define FST_MONITOR     3               /* Monitor only (raw packet reception) */
+#define FST_RAW         4               /* Two way raw packets */
+#define FST_GEN_HDLC    5               /* Using "Generic HDLC" module */
+
+/* "internalClock" */
+#define INTCLK          1
+#define EXTCLK          0
+
+/* "v24IpSts" bitmask */
+#define IPSTS_CTS       0x00000001      /* Clear To Send (Indicate for X.21) */
+#define IPSTS_INDICATE  IPSTS_CTS
+#define IPSTS_DSR       0x00000002      /* Data Set Ready (T2P Port A) */
+#define IPSTS_DCD       0x00000004      /* Data Carrier Detect */
+#define IPSTS_RI        0x00000008      /* Ring Indicator (T2P Port A) */
+#define IPSTS_TMI       0x00000010      /* Test Mode Indicator (Not Supported)*/
+
+/* "v24OpSts" bitmask */
+#define OPSTS_RTS       0x00000001      /* Request To Send (Control for X.21) */
+#define OPSTS_CONTROL   OPSTS_RTS
+#define OPSTS_DTR       0x00000002      /* Data Terminal Ready */
+#define OPSTS_DSRS      0x00000004      /* Data Signalling Rate Select (Not
+                                         * Supported) */
+#define OPSTS_SS        0x00000008      /* Select Standby (Not Supported) */
+#define OPSTS_LL        0x00000010      /* Maintenance Test (Not Supported) */
+
+/* "cardMode" bitmask */
+#define CARD_MODE_IDENTIFY      0x0001
+
+/*
+ * TxRx Start Parameters
+ */
+#define START_TX 1
+#define START_RX 2
+#define START_TX_AND_RX (START_TX | START_RX)
+#define START_DEFAULT START_TX_AND_RX
+
+/* 
+ * Constants for T1/E1 configuration
+ */
+
+/*
+ * Clock source
+ */
+#define CLOCKING_SLAVE       0
+#define CLOCKING_MASTER      1
+
+/*
+ * Framing
+ */
+#define FRAMING_E1           0
+#define FRAMING_J1           1
+#define FRAMING_T1           2
+
+/*
+ * Structure
+ */
+#define STRUCTURE_UNFRAMED   0
+#define STRUCTURE_E1_DOUBLE  1
+#define STRUCTURE_E1_CRC4    2
+#define STRUCTURE_E1_CRC4M   3
+#define STRUCTURE_T1_4       4
+#define STRUCTURE_T1_12      5
+#define STRUCTURE_T1_24      6
+#define STRUCTURE_T1_72      7
+
+/*
+ * Interface
+ */
+#define INTERFACE_RJ48C      0
+#define INTERFACE_BNC        1
+
+/*
+ * Coding
+ */
+
+#define CODING_HDB3          0
+#define CODING_NRZ           1
+#define CODING_CMI           2
+#define CODING_CMI_HDB3      3
+#define CODING_CMI_B8ZS      4
+#define CODING_AMI           5
+#define CODING_AMI_ZCS       6
+#define CODING_B8ZS          7
+
+/*
+ * Line Build Out
+ */
+#define LBO_0dB              0
+#define LBO_7dB5             1
+#define LBO_15dB             2
+#define LBO_22dB5            3
+
+/*
+ * Range for long haul t1 > 655ft
+ */
+#define RANGE_0_133_FT       0
+#define RANGE_0_40_M         RANGE_0_133_FT
+#define RANGE_133_266_FT     1
+#define RANGE_40_81_M        RANGE_133_266_FT
+#define RANGE_266_399_FT     2
+#define RANGE_81_122_M       RANGE_266_399_FT
+#define RANGE_399_533_FT     3
+#define RANGE_122_162_M       RANGE_399_533_FT
+#define RANGE_533_655_FT     4
+#define RANGE_162_200_M      RANGE_533_655_FT
+/*
+ * Receive Equaliser
+ */
+#define EQUALIZER_SHORT      0
+#define EQUALIZER_LONG       1
+
+/*
+ * Loop modes
+ */
+#define LOOP_NONE            0
+#define LOOP_LOCAL           1
+#define LOOP_PAYLOAD_EXC_TS0 2
+#define LOOP_PAYLOAD_INC_TS0 3
+#define LOOP_REMOTE          4
+
+/*
+ * Buffer modes
+ */
+#define BUFFER_2_FRAME       0
+#define BUFFER_1_FRAME       1
+#define BUFFER_96_BIT        2
+#define BUFFER_NONE          3
+
+/*
+ * DSL Equipment types
+ */
+#define EQUIP_TYPE_REMOTE    0
+#define EQUIP_TYPE_CENTRAL   1
+
+/*
+ * DSL Operating modes
+ */
+#define ANNEX_A              1    /* US */
+#define ANNEX_B              0    /* EU */
+
+/*
+ * DSL ATM Encapsulation methods
+ */
+#define ENCAP_PPP            0
+#define ENCAP_MPOA           1
+#define MPOA_HEADER_LEN      8
+
+/*
+ * DSL Test Modes
+ */
+#define TEST_MODE_NONE                        0
+#define TEST_MODE_DEFAULT TEST_MODE_NONE
+
+#define TEST_MODE_ALTERNATING_SINGLE_PULSE    1
+#define TEST_MODE_ANALOG_TRANSPARENT_LOOP     4
+#define TEST_MODE_ANALOG_NON_TRANSPARENT_LOOP 8
+#define TEST_MODE_TRANSMIT_SC_SR              9
+#define TEST_MODE_TRANSMIT_TC_PAM_SCRONE      10
+#define TEST_MODE_LINE_DRIVER_NO_SIGNAL       11
+#define TEST_MODE_AGC_TO_LINE_DRIVER_LOOP     12
+
+#define TEST_MODE_LOOP_TDM_TO_LINE            16
+#define TEST_MODE_LOOP_PAYLOAD_TO_LINE        17
+
+/*      Debug support
+ *
+ *      These should only be enabled for development kernels, production code
+ *      should define FST_DEBUG=0 in order to exclude the code.
+ *      Setting FST_DEBUG=1 will include all the debug code but in a disabled
+ *      state, use the FSTSETCONF ioctl to enable specific debug actions, or
+ *      FST_DEBUG can be set to prime the debug selection.
+ */
+#define FST_DEBUG       0x0000
+#if FST_DEBUG
+
+extern int fst_debug_mask;              /* Bit mask of actions to debug, bits
+                                         * listed below. Note: Bit 0 is used
+                                         * to trigger the inclusion of this
+                                         * code, without enabling any actions.
+                                         */
+#define DBG_INIT        0x0002          /* Card detection and initialisation */
+#define DBG_OPEN        0x0004          /* Open and close sequences */
+#define DBG_PCI         0x0008          /* PCI config operations */
+#define DBG_IOCTL       0x0010          /* Ioctls and other config */
+#define DBG_INTR        0x0020          /* Interrupt routines (be careful) */
+#define DBG_TX          0x0040          /* Packet transmission */
+#define DBG_RX          0x0080          /* Packet reception */
+#define DBG_CMD         0x0100          /* Port command issuing */
+#define DBG_ATM         0x0200          /* ATM processing */
+#define DBG_TTY         0x0400          /* PPPd processing */
+#define DBG_ASS         0x0001          /* Assert like statements. Code that
+                                         * should never be reached, if you see
+                                         * one of these then I've been an ass
+                                         */
+#endif  /* FST_DEBUG */
+
diff --git a/lib/farsync/windows/CVS/Entries b/lib/farsync/windows/CVS/Entries
new file mode 100644
index 0000000..eb6576c
--- /dev/null
+++ b/lib/farsync/windows/CVS/Entries
@@ -0,0 +1,4 @@
+/fscfg.h/1.1.1.1/Wed Sep  9 22:14:15 2009//
+/sdci.h/1.1.1.1/Wed Sep  9 22:14:15 2009//
+/smcuser.h/1.1.1.1/Wed Sep  9 22:14:15 2009//
+D
diff --git a/lib/farsync/windows/CVS/Repository b/lib/farsync/windows/CVS/Repository
new file mode 100644
index 0000000..c77b5cb
--- /dev/null
+++ b/lib/farsync/windows/CVS/Repository
@@ -0,0 +1 @@
+crc-dabmux/lib/farsync/windows
diff --git a/lib/farsync/windows/CVS/Root b/lib/farsync/windows/CVS/Root
new file mode 100644
index 0000000..9e5f945
--- /dev/null
+++ b/lib/farsync/windows/CVS/Root
@@ -0,0 +1 @@
+:pserver:pascal@mmlab.dgbt.crc.ca:/home/cvsroot
diff --git a/lib/farsync/windows/fscfg.h b/lib/farsync/windows/fscfg.h
new file mode 100644
index 0000000..7a13884
--- /dev/null
+++ b/lib/farsync/windows/fscfg.h
@@ -0,0 +1,574 @@
+/*******************************************************************************
+*                                                                 
+* Program     : FarSync (generic)
+*                                                                 
+* File        : fscfg.h
+*                                                                 
+* Description : Common FarSync Configuration Definitions used through the 
+*               FarSync PC-based  modules
+*                                                    
+* Modifications
+*
+* Version 2.1.0  01Mar01  WEB  Add device and port configuration values 
+*                09Mar01  WEB  Add Fswan hwid
+* Version 2.2.0  18Jul01  WEB  Certification candidate
+*                22Oct01  MJD  Added Transparent Mode support - define 
+*                              names and values for Transparent Mode and
+*                              Buffer Length parameters.
+* Version 2.2.6  26Oct01  WEB  Add name for devices use only for SDCI applications.
+* Version 2.3.0  28Nov01  WEB  Add minnow ids + DeviceIDToCardID map
+* Version 2.3.1  08Apr02  WEB  Change min buffer length from 62 to 2
+* Version 2.3.2  27Aug02  WEB  Rationalised
+* Version 3.0.2  05Nov02  WEB  Add 'U' to DeviceIDToCardID map
+* Version 3.2.0  09Dec02  WEB  Add Invert Rx Clock, Dual Clocking & DMA definitions
+* Version 3.4.0  26Oct04  WEB  Add fstap definitions
+* Version 3.5.0  11Nov04  WEB  Add te1 definitions
+* Version 4.0.0  18Feb05  WEB  Add configurable number and size of buffers, start 
+*                              tx/rx
+* Version 4.0.1  03Mar05  WEB  Add extended clocking definitions
+* Version 4.0.2  17Mar05  WEB  Correct FS_LINE_INTERFACE_MAX - should be V35
+* Version 4.1.0  24Jun05  WEB  Add new T4E defs
+* Version 4.2.0  12Sep05  WEB  Add FS_NDEVICE_CLASS i.e. support for T4E MkII
+*                              Reduce FS_LINE_RATE_MIN to 300
+*
+*******************************************************************************/
+
+#ifndef __FSCFG_H_
+#define __FSCFG_H_
+
+#define SMCUSER_PACKING 1
+#include "smcuser.h"  // Values also used in the adapter window interface */
+
+// PCI IDs
+#define FS_VENDOR_ID 0x1619
+#define FS_DEVICE_CLASS 0x0400  // ie. 0400 .. 04FF
+#define FS_TDEVICE_CLASS FS_DEVICE_CLASS
+
+// FarSync card classes/Device ID ranges
+#define FS_MDEVICE_CLASS 0x0500  // ie. 0500 .. 05FF
+#define FS_VDEVICE_CLASS 0x0000  // ie. 0000 .. 00FF
+#define FS_UDEVICE_CLASS 0x0600  // ie. 0600 .. 06FF
+#define FS_EDEVICE_CLASS 0x1600  // ie. 1600 .. 16FF
+#define FS_NDEVICE_CLASS 0x3600  // ie. 3600 .. 36FF
+#define FS_DDEVICE_CLASS 0x1700  // ie. 1700 .. 17FF
+
+#define FS_CARDID_MASK  0xFF00
+
+// Class maps
+struct _DEVICEIDTOCARDID// e.g. 0400 -> T, 0500 -> M, 0600 -> T
+{
+  ULONG uDeviceID;
+  char  cCardID;
+};
+#define DEVICEIDTOCARDID struct _DEVICEIDTOCARDID
+#ifdef FS_DECLARE_CFG_ARRAYS
+DEVICEIDTOCARDID DeviceIDToCardID[] = { {FS_TDEVICE_CLASS, 'T'},
+                                        {FS_MDEVICE_CLASS, 'M'},
+                                        {FS_VDEVICE_CLASS, 'V'},
+                                        {FS_UDEVICE_CLASS, 'T'},
+                                        {FS_EDEVICE_CLASS, 'T'},
+                                        {FS_DDEVICE_CLASS, 'D'},
+                                        {FS_NDEVICE_CLASS, 'T'}
+                                      };
+typedef struct _DEVICEIDTOCARDID2
+{
+  ULONG uDeviceID;
+  char  cCardID;
+} DEVICEIDTOCARDID2;  // e.g. 0400 -> P, 0500 -> P, 0600 -> U
+#endif
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+DEVICEIDTOCARDID DeviceIDToCardID2[] = { {FS_TDEVICE_CLASS, 'P'},
+                                         {FS_MDEVICE_CLASS, 'P'},
+                                         {FS_VDEVICE_CLASS, 'P'},
+                                         {FS_UDEVICE_CLASS, 'U'},
+                                         {FS_EDEVICE_CLASS, 'E'},
+                                         {FS_DDEVICE_CLASS, 'S'},
+                                         {FS_NDEVICE_CLASS, 'E'}
+                                       };
+#else
+DEVICEIDTOCARDID DeviceIDToCardID2[];
+#endif
+
+#define FS_FSWAN_HWID  "fsvbus\\FS_TXP-00"   // must match value in .inf
+#define FS_VBUS_PREFIX_U L"fsv"
+
+// Limits required for adapter/port enumeration
+#define FS_MAX_ADAPTERS      100
+#define FS_MAX_SYNC_ADAPTERS  10
+#define FS_MAX_PORTS          MAX_PORTS
+
+#define FS_MAX_DEVICE_NAME  32 // number of WCHARs required to accomodate the longest device name 
+                               // e.g. \Device\SYNCH, \DosDevices\SYNC1 or \DosDevices\FSPPP0006
+#define FS_DEVICE_PREFIX     "SYNC"
+#define FS_DEVICE_PREFIX_U  L"SYNC"
+
+#define FS_PPP_DEVICE_NAME  "FSPPP%s"  // name of farsynct device when in ppp mode
+
+#define FS_SDCI_DEVICE_NAME  "SDCI%s"  // name of farsynct device when in sdci mode
+
+#define FS_PORT_DEVICE_NAME   "PortDeviceName"  // stores name of farsynct port to use
+#define LFS_PORT_DEVICE_NAME  L"PortDeviceName" // required for use in ndiswan driver
+
+#define FS_MAX_PARAM_NAME 128  // max number of chars in FS_LINE_NAME_PARAM_NAME etc.
+
+/* Line name values */
+#define FS_LINE_NAME_PARAM_NAME   "Port%u_%u_Name"
+#define FS_LINE_NAME_MAX_CHARS    16
+#define FS_LINE_NAME_DEF          "FSWAN_%u"
+#define FS_PORT_NAME_DEF          "Port %c"
+#define FS_PORT_NAME_PARAM_NAME   "Port%u_Name"
+
+/* Line interface values */
+#define FS_LINE_INTERFACE_PARAM_NAME    "Port%u_%u_Interface"
+#define FS_LINE_INTERFACE_MIN           V24
+#define FS_LINE_INTERFACE_V24           V24
+#define FS_LINE_INTERFACE_X21           X21
+#define FS_LINE_INTERFACE_X21D          X21D
+#define FS_LINE_INTERFACE_V35           V35
+#define FS_LINE_INTERFACE_RS530_449     RS530_449
+// Note: Specifying MAX as X21D intentionally makes RS530_449 not accessible to the current client GUIs
+#define FS_LINE_INTERFACE_MAX           RS530_449
+#define FS_LINE_INTERFACE_DEF           X21    
+#define FS_LINE_INTERFACE_MAX_CHARS     7
+#define FS_PORT_INTERFACE_PARAM_NAME    "Port%u_Interface"
+#define FS_PORT_INTERFACE_PARAM_NAME_U L"Port%u_Interface"
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsT4EInterfaceTypesTable[]    = {"Auto", "V.24", "X.21", "V.35", "X.21 (Dual-Clocking)", "RS530/449", 0};
+char* szFsT4EInterfaceTypesTable2[]   = {"Auto", "V.24", "X.21", "V.35", "X.21D", "RS530", 0};
+ULONG uFsT4EInterfaceTypesTableVals[] = {AUTO, V24, X21, V35, X21D, RS530_449, 0};
+char* szFsInterfaceTypesTable[]       = {"Auto", "V.24", "X.21", "V.35", "X.21 (Dual-Clocking)", 0};
+char* szFsM1PInterfaceTypesTable[]    = {"Auto", "V.24", "X.21", "V.35", 0};
+#else
+char* szFsT4EInterfaceTypesTable[];
+char* szFsT4EInterfaceTypesTable2[];
+ULONG uFsT4EInterfaceTypesTableVals[];
+char* szFsInterfaceTypesTable[];
+char* szFsM1PInterfaceTypesTable[];
+#endif
+
+/* Line rate values */
+#define FS_LINE_RATE_PARAM_NAME    "Port%u_%u_Rate"
+#define FS_LINE_RATE_MIN           300
+#define FS_LINE_RATE_MAX           8192000
+#define FS_LINE_RATE_DEF           64000
+#define FS_LINE_RATE_MAX_CHARS     7
+#define FS_PORT_RATE_PARAM_NAME    "Port%u_Rate"
+#define FS_PORT_RATE_PARAM_NAME_U L"Port%u_Rate"
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+ULONG uFsRateTable[] = {1200,     2400,    4800,    9600,    
+                        19200,    38400,   64000,   76800,  
+                        128000,   153600,  256000,  307200,
+                        512000,   614400,  1024000, 2048000,        
+                        4096000,  8192000, 0 };
+#else
+ULONG uFsRateTable[];
+#endif
+
+/* Line clocking values */
+#define FS_LINE_CLOCKING_PARAM_NAME    "Port%u_%u_InternalClocking"
+#define FS_LINE_CLOCKING_MIN           EXTCLK
+#define FS_LINE_CLOCKING_EXTERNAL      EXTCLK
+#define FS_LINE_CLOCKING_INTERNAL      INTCLK
+#define FS_LINE_CLOCKING_MAX           INTCLK
+#define FS_LINE_CLOCKING_DEF           EXTCLK
+#define FS_LINE_CLOCKING_MAX_CHARS     8
+#define FS_PORT_CLOCKING_PARAM_NAME    "Port%u_InternalClocking"
+#define FS_PORT_CLOCKING_PARAM_NAME_U L"Port%u_InternalClocking"
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsClockingTypesTable[] = {"External", "Internal", 0}; // maps onto FALSE, TRUE
+#else
+char* szFsClockingTypesTable[];
+#endif
+
+/* Transparent mode values */
+#define FS_LINE_TRANSPARENT_MIN           FALSE
+#define FS_LINE_TRANSPARENT_MAX           TRUE
+#define FS_LINE_TRANSPARENT_DEF           FALSE
+#define FS_PORT_TRANSPARENT_PARAM_NAME    "Port%u_TransparentMode"
+#define FS_PORT_TRANSPARENT_PARAM_NAME_U L"Port%u_TransparentMode"
+
+/* HDLC/Transparent mode values */
+#define FS_LINE_MODE_HDLC          0
+#define FS_LINE_MODE_TRANSPARENT   1
+#define FS_LINE_MODE_MIN           FS_LINE_MODE_HDLC          
+#define FS_LINE_MODE_MAX           FS_LINE_MODE_TRANSPARENT
+#define FS_LINE_MODE_DEF           FS_LINE_MODE_HDLC
+#define FS_LINE_MODE_MAX_CHARS     12
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsModeTypesTable[] = {"HDLC", "Transparent", 0};
+#else
+char* szFsModeTypesTable[];
+#endif
+
+/* Buffer length values */
+#define FS_LINE_BUFFER_MIN           2
+#define FS_LINE_BUFFER_MAX           64*1024
+#define FS_LINE_BUFFER_DEF           8*1024
+#define FS_PORT_BUFFER_PARAM_NAME       "Port%u_BufferLength"
+#define FS_PORT_BUFFER_PARAM_NAME_U    L"Port%u_BufferLength"
+#define FS_PORT_TX_BUFFER_PARAM_NAME    "Port%u_TxBufferLength"
+#define FS_PORT_TX_BUFFER_PARAM_NAME_U L"Port%u_TxBufferLength"
+#define FS_PORT_RX_BUFFER_PARAM_NAME    "Port%u_RxBufferLength"
+#define FS_PORT_RX_BUFFER_PARAM_NAME_U L"Port%u_RxBufferLength"
+
+// Note: UNDEF values means that the vars are ignored (i.e. different from DEFault values)
+
+/* Invert Rx clock values */
+#define FS_PORT_INVERT_RX_CLOCK_MIN           FALSE
+#define FS_PORT_INVERT_RX_CLOCK_MAX           TRUE
+#define FS_PORT_INVERT_RX_CLOCK_DEF           FALSE
+#define FS_PORT_INVERT_RX_CLOCK_UNDEF         0xFFFFFFFF
+#define FS_PORT_INVERT_RX_CLOCK_PARAM_NAME    "Port%u_InvertRxClock"
+#define FS_PORT_INVERT_RX_CLOCK_PARAM_NAME_U L"Port%u_InvertRxClock"
+
+/* Dual Clocking values */
+#define FS_PORT_DUAL_CLOCKING_DEF           FALSE
+#define FS_PORT_DUAL_CLOCKING_PARAM_NAME    "Port%u_DualClocking"
+#define FS_PORT_DUAL_CLOCKING_PARAM_NAME_U L"Port%u_DualClocking"
+
+/* Tx DMA values */
+#define FS_PORT_TX_DMA_UNDEF         0xFFFFFFFF
+#define FS_PORT_TX_DMA_PARAM_NAME    "Port%u_TxDMA"
+#define FS_PORT_TX_DMA_PARAM_NAME_U L"Port%u_TxDMA"
+
+/* Rx DMA values */
+#define FS_PORT_RX_DMA_UNDEF         0xFFFFFFFF
+#define FS_PORT_RX_DMA_PARAM_NAME    "Port%u_RxDMA"
+#define FS_PORT_RX_DMA_PARAM_NAME_U L"Port%u_RxDMA"
+
+#define FS_PORT_DMA_MAX FSDMAMODE_ON
+#define FS_PORT_DMA_MIN FSDMAMODE_OFF
+#define FS_PORT_DMA_DEF FSDMAMODE_OFF
+
+/* Number of Tx buffers */
+#define FS_PORT_TX_NUM_BUFFERS_MIN           2
+#define FS_PORT_TX_NUM_BUFFERS_MAX           128
+#define FS_PORT_TX_NUM_BUFFERS_DEF           8
+#define FS_PORT_TX_NUM_BUFFERS_UNDEF         0xFFFFFFFF
+#define FS_PORT_TX_NUM_BUFFERS_PARAM_NAME    "Port%u_TxNumBuffers"
+#define FS_PORT_TX_NUM_BUFFERS_PARAM_NAME_U L"Port%u_TxNumBuffers"
+
+/* Number of Rx buffers */
+#define FS_PORT_RX_NUM_BUFFERS_MIN           2
+#define FS_PORT_RX_NUM_BUFFERS_MAX           128
+#define FS_PORT_RX_NUM_BUFFERS_DEF           8
+#define FS_PORT_RX_NUM_BUFFERS_UNDEF         0xFFFFFFFF
+#define FS_PORT_RX_NUM_BUFFERS_PARAM_NAME    "Port%u_RxNumBuffers"
+#define FS_PORT_RX_NUM_BUFFERS_PARAM_NAME_U L"Port%u_RxNumBuffers"
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsNumBuffersTable[] = {"2", "4", "8", "16", "32", "64", "128", 0};
+#else
+char* szFsNumBuffersTable[];
+#endif
+
+/* Encoding values */
+#define FS_PORT_ENCODING_PARAM_NAME     "Port%u_Encoding"
+#define FS_PORT_ENCODING_PARAM_NAME_U  L"Port%u_Encoding"
+#define FS_PORT_ENCODING_NRZ  0x80
+#define FS_PORT_ENCODING_NRZI 0xa0
+#define FS_PORT_ENCODING_FM0  0xc0
+#define FS_PORT_ENCODING_FM1  0xd0
+#define FS_PORT_ENCODING_MAN  0xe0
+#define FS_PORT_ENCODING_MIN  FS_PORT_ENCODING_NRZ
+#define FS_PORT_ENCODING_MAX  FS_PORT_ENCODING_MAN
+#define FS_PORT_ENCODING_DEF  FS_PORT_ENCODING_NRZ
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsEncodingTypesTable[] = {"NRZ", "NRZI", "FM0", "FM1", "MAN", 0};
+#else
+char* szFsEncodingTypesTable[];
+#endif
+
+
+/* Registry Config Names */
+#define FS_EVENT_SUBKEY_NAME      "SYSTEM\\CurrentControlSet\\Services\\EventLog\\System\\farsynct"
+#define EVENT_VAR_TYPES_SUPPORTED "TypesSupported"
+#define EVENT_VAR_MESSAGE_FILE    "EventMessageFile"
+#define FS_MESSAGE_FILE           "%SystemRoot%\\System32\\IOLOGMSG.DLL;%SystemRoot%\\System32\\Drivers\\farsynct.sys"
+
+#define REG_SERVICES_ROOT_U       L"\\REGISTRY\\Machine\\SYSTEM\\CurrentControlSet\\Services\\"
+#define REG_MACHINE_ROOT_U        L"\\REGISTRY\\Machine\\"
+#define REG_FSWAN_CONFIG_PATH_U   L"SOFTWARE\\FarSite\\FSWAN"
+
+/* Pool Tags */
+
+#define FARSYNCT_TAG1  '1TsF'
+#define FARSYNCM_TAG1  '1PsF'
+
+#define FSX25MDM_TAG1  '1MsF'
+
+#define FSKUTL_TAG1 '1UsF'
+
+#define FSWAN_TAG1  '1WsF'
+#define FSWAN_TAG2  '2WsF'
+
+/* fstap config */
+
+#define FSTAP_DEVICENAME_PARAM_NAME        "DeviceName"
+#define FSTAP_PORT_PARAM_NAME              "Port"
+#define FSTAP_IGNORE_SIGNALS_DEF           FALSE
+#define FSTAP_IGNORE_SIGNALS_PARAM_NAME    "IgnoreSignals"
+#define FSTAP_ENABLE_MONITORING_DEF        TRUE
+#define FSTAP_ENABLE_MONITORING_PARAM_NAME "EnableMonitoring"
+
+/* te1 config */
+
+#define FS_PORT_FRAMING_MIN           FRAMING_E1
+#define FS_PORT_FRAMING_MAX           FRAMING_T1
+#define FS_PORT_FRAMING_PARAM_NAME    "Port%u_Framing"
+#define FS_PORT_FRAMING_PARAM_NAME_U  L"Port%u_Framing"
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsFramingTypesTable[] = {"E1", "J1", "T1", 0};
+#else
+char* szFsFramingTypesTable[];
+#endif
+
+#define FS_PORT_ECLOCKING_MIN           CLOCKING_SLAVE
+#define FS_PORT_ECLOCKING_MAX           CLOCKING_MASTER
+#ifdef notreq
+#define FS_PORT_ECLOCKING_PARAM_NAME    "Port%u_Clocking"   
+#define FS_PORT_ECLOCKING_PARAM_NAME_U  L"Port%u_Clocking"   
+#endif
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsEClockingTypesTable[] = {"Slave", "Master", 0};
+#else
+char* szFsEClockingTypesTable[];
+#endif
+
+#define FS_PORT_DATARATE_MIN              8000
+#define FS_PORT_E1_DATARATE_MAX           2048000
+#define FS_PORT_T1_DATARATE_MAX           1544000
+#ifdef notreq
+#define FS_PORT_DATARATE_PARAM_NAME    "Port%u_DataRate"   
+#define FS_PORT_DATARATE_PARAM_NAME_U  L"Port%u_DataRate"   
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsDataRateTable[] = {"1", "2", 0};
+#else
+char* szFsDataRateTable[];
+#endif
+#endif
+
+#define FS_PORT_STRUCTURE_MIN           STRUCTURE_UNFRAMED
+#define FS_PORT_STRUCTURE_MAX           STRUCTURE_T1_72
+#define FS_PORT_STRUCTURE_PARAM_NAME    "Port%u_Structure"   
+#define FS_PORT_STRUCTURE_PARAM_NAME_U  L"Port%u_Structure"   
+
+
+#define STRUCTURE_UNFRAMED   0
+#define STRUCTURE_E1_DOUBLE  1
+#define STRUCTURE_E1_CRC4    2
+#define STRUCTURE_E1_DEFAULT STRUCTURE_E1_CRC4
+#define STRUCTURE_DEFAULT    STRUCTURE_E1_CRC4
+#define STRUCTURE_E1_CRC4M   3
+#define STRUCTURE_T1_4       4
+#define STRUCTURE_T1_12      5
+#define STRUCTURE_T1_24      6
+#define STRUCTURE_T1_DEFAULT STRUCTURE_T1_24
+#define STRUCTURE_T1_72      7
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsE1StructureTypesTable[] = {"Unframed", "Double", "CRC4", "CRC4M", 0};
+int iFsE1StructureValuesTable[] = {STRUCTURE_UNFRAMED, STRUCTURE_E1_DOUBLE, STRUCTURE_E1_CRC4, STRUCTURE_E1_CRC4M, -1};
+char* szFsT1StructureTypesTable[] = {"Unframed", "F4 (FT)", "F12 (D3/D4, SF)", "F24 (D5, Fe, ESF)", "F72 (SLC96)", 0};
+int iFsT1StructureValuesTable[] = {STRUCTURE_UNFRAMED, STRUCTURE_T1_4, STRUCTURE_T1_12, STRUCTURE_T1_24, STRUCTURE_T1_72, -1};
+#else
+char* szFsE1StructureTypesTable[];
+int iFsE1StructureValuesTable[];
+char* szFsT1StructureTypesTable[];
+int iFsT1StructureValuesTable[];
+#endif
+
+#define FS_PORT_IFACE_MIN           INTERFACE_RJ48C
+#define FS_PORT_IFACE_MAX           INTERFACE_BNC
+#define FS_PORT_IFACE_PARAM_NAME    "Port%u_Iface"   
+#define FS_PORT_IFACE_PARAM_NAME_U  L"Port%u_Iface"   
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsE1IfaceTypesTable[] = {"RJ48C", "BNC", 0};
+int iFsE1IfaceValuesTable[] = {INTERFACE_RJ48C, INTERFACE_BNC, -1};
+char* szFsT1IfaceTypesTable[] = {"RJ48C", 0};
+int iFsT1IfaceValuesTable[] = {INTERFACE_RJ48C, -1};
+#else
+char* szFsE1IfaceTypesTable[];
+int iFsE1IfaceValuesTable[];
+char* szFsT1IfaceTypesTable[];
+int iFsT1IfaceValuesTable[];
+#endif
+
+#define FS_PORT_CODING_MIN           CODING_HDB3
+#define FS_PORT_CODING_MAX           CODING_B8ZS
+#define FS_PORT_CODING_PARAM_NAME    "Port%u_Coding"   
+#define FS_PORT_CODING_PARAM_NAME_U  L"Port%u_Coding"   
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+//char* szFsE1CodingTypesTable[] = {"HDB3", "NRZ", "CMI", "CMI-HDB3", "AMI", 0};
+//int iFsE1CodingValuesTable[] = {CODING_HDB3, CODING_NRZ, CODING_CMI, CODING_CMI_HDB3, CODING_AMI, -1};
+char* szFsE1CodingTypesTable[] = {"HDB3", "AMI", 0};
+int iFsE1CodingValuesTable[] = {CODING_HDB3, CODING_AMI, -1};
+//char* szFsT1CodingTypesTable[] = {"NRZ", "CMI", "CMI_B8ZS", "AMI", "AMI-ZCS", "B8ZS", 0};
+//int iFsT1CodingValuesTable[] = {CODING_NRZ, CODING_CMI, CODING_CMI_B8ZS, CODING_AMI, CODING_AMI_ZCS, CODING_B8ZS, -1};
+char* szFsT1CodingTypesTable[] = {"AMI", "AMI-ZCS", "B8ZS", 0};
+int iFsT1CodingValuesTable[] = {CODING_AMI, CODING_AMI_ZCS, CODING_B8ZS, -1};
+#else
+char* szFsE1CodingTypesTable[];
+int iFsE1CodingValuesTable[];
+char* szFsT1CodingTypesTable[];
+int iFsT1CodingValuesTable[];
+#endif
+
+#define FS_PORT_LBO_MIN           LBO_0dB
+#define FS_PORT_LBO_MAX           LBO_22dB5
+#define FS_PORT_LBO_PARAM_NAME    "Port%u_LBO"   
+#define FS_PORT_LBO_PARAM_NAME_U  L"Port%u_LBO"   
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsLBOTypesTable[] = {"0", "7.5", "15", "22.5", 0};
+#else
+char* szFsLBOTypesTable[];
+#endif
+
+#define FS_PORT_EQUALIZER_MIN           EQUALIZER_SHORT
+#define FS_PORT_EQUALIZER_MAX           EQUALIZER_LONG
+#define FS_PORT_EQUALIZER_PARAM_NAME    "Port%u_Equalizer"   
+#define FS_PORT_EQUALIZER_PARAM_NAME_U  L"Port%u_Equalizer"   
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsEqualizerTypesTable[] = {"Short", "Long", 0};
+#else
+char* szFsEqualizerTypesTable[];
+#endif
+
+#define FS_PORT_LOOP_MODE_MIN           LOOP_NONE
+#define FS_PORT_LOOP_MODE_MAX           LOOP_REMOTE
+#define FS_PORT_LOOP_MODE_PARAM_NAME    "Port%u_LoopMode"   
+#define FS_PORT_LOOP_MODE_PARAM_NAME_U  L"Port%u_LoopMode"   
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsLoopModeTypesTable[] = {"None", "Local", "Payload (excl TS0)", "Payload (incl TS0)", "Remote", 0};
+#else
+char* szFsLoopModeTypesTable[];
+#endif
+
+#define FS_PORT_RANGE_MIN           RANGE_0_40_M
+#define FS_PORT_RANGE_MAX           RANGE_162_200_M
+#define FS_PORT_RANGE_PARAM_NAME    "Port%u_Range"   
+#define FS_PORT_RANGE_PARAM_NAME_U  L"Port%u_Range"   
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsRangeTypesTable[] = {"0-133ft (0-40m)", "133-266ft (40-81m)", "266-399ft (81-122m)", "399-533ft (122-162m)", "533-655ft (162-200m)", 0};
+#else
+char* szFsRangeTypesTable[];
+#endif
+
+#define FS_PORT_BUFFER_MODE_MIN           BUFFER_2_FRAME
+#define FS_PORT_BUFFER_MODE_MAX           BUFFER_NONE
+#define FS_PORT_TX_BUFFER_MODE_PARAM_NAME    "Port%u_TxBufferMode"   
+#define FS_PORT_TX_BUFFER_MODE_PARAM_NAME_U  L"Port%u_TxBufferMode"   
+#define FS_PORT_RX_BUFFER_MODE_PARAM_NAME    "Port%u_RxBufferMode"   
+#define FS_PORT_RX_BUFFER_MODE_PARAM_NAME_U  L"Port%u_RxBufferMode"   
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsBufferModeTypesTable[] = {"2 Frame", "1 Frame", "96 bit", "None", 0};
+#else
+char* szFsBufferModeTypesTable[];
+#endif
+
+#define FS_PORT_STARTING_TS_MIN           0
+#define FS_PORT_STARTING_TS_MAX           31
+#define FS_PORT_STARTING_TS_PARAM_NAME    "Port%u_StartingTs"   
+#define FS_PORT_STARTING_TS_PARAM_NAME_U  L"Port%u_StartingTs"   
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsE1StartingTSTypesTable[] = { "1",  "2",  "3",  "4",  "5",  "6",  "7",  "8",  "9", 
+                                    "10", "11", "12", "13", "14", "15", "16", "17", "18", "19", 
+                                    "20", "21", "22", "23", "24", "25", "26", "27", "28", "29", 
+                                    "30", "31",
+                                    0};
+char* szFsT1StartingTSTypesTable[] = { "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",  "8",  "9", 
+                                    "10", "11", "12", "13", "14", "15", "16", "17", "18", "19", 
+                                    "20", "21", "22", "23", 
+                                    0};
+#else
+char* szFsE1StartingTSTypesTable[];
+char* szFsT1StartingTSTypesTable[];
+#endif
+
+#define FS_PORT_LOS_THRESHOLD_MIN           0
+#define FS_PORT_LOS_THRESHOLD_MAX           7
+#define FS_PORT_LOS_THRESHOLD_PARAM_NAME    "Port%u_LOSThreshold"   
+#define FS_PORT_LOS_THRESHOLD_PARAM_NAME_U  L"Port%u_LOSThreshold"   
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsLOSThresholdTypesTable[] = { "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",  0};
+#else
+char* szFsLOSThresholdTypesTable[];
+#endif
+
+#define FS_PORT_ENABLE_IDLE_CODE_MIN           0
+#define FS_PORT_ENABLE_IDLE_CODE_MAX           1
+#define FS_PORT_ENABLE_IDLE_CODE_PARAM_NAME    "Port%u_EnableIdleCode"   
+#define FS_PORT_ENABLE_IDLE_CODE_PARAM_NAME_U  L"Port%u_EnableIdleCode"   
+
+#define FS_PORT_IDLE_CODE_MIN           0
+#define FS_PORT_IDLE_CODE_MAX           0xff
+#define FS_PORT_IDLE_CODE_PARAM_NAME    "Port%u_IdleCode"   
+#define FS_PORT_IDLE_CODE_PARAM_NAME_U  L"Port%u_IdleCode"   
+
+#define FS_PORT_START_TXRX_MIN           0
+#define FS_PORT_START_TXRX_DEF           START_TX_AND_RX
+#define FS_PORT_START_TXRX_MAX           START_TX_AND_RX
+#define FS_PORT_START_TXRX_PARAM_NAME    "Port%u_StartTxRx"   
+#define FS_PORT_START_TXRX_PARAM_NAME_U  L"Port%u_StartTxRx"   
+
+#define FS_PORT_CLOCK_SOURCE_MIN           FS_CLOCK_REFERENCE_OSCILLATOR
+#define FS_PORT_CLOCK_SOURCE_DEF           FS_CLOCK_REFERENCE_OSCILLATOR
+#define FS_PORT_CLOCK_SOURCE_MAX           FS_CLOCK_REFERENCE_CTBUS
+#define FS_PORT_CLOCK_SOURCE_PARAM_NAME    "Port%u_ClockSource"   
+#define FS_PORT_CLOCK_SOURCE_PARAM_NAME_U  L"Port%u_ClockSource"   
+
+#ifdef FS_DECLARE_CFG_ARRAYS
+char* szFsClockSourceTable[] = {"Local Oscillator", "CT_BUS", 0};
+#else
+char* szFsClockSourceTable[];
+#endif
+
+#define FS_SERIAL_EXTENDED_CLOCKING_DEF           FALSE
+#define FS_SERIAL_EXTENDED_CLOCKING_PARAM_NAME    "Port%u_ExtendedClocking"   
+#define FS_SERIAL_EXTENDED_CLOCKING_PARAM_NAME_U  L"Port%u_ExtendedClocking"
+
+#define FS_SERIAL_INT_TX_CLOCK_DEF           FALSE
+#define FS_SERIAL_INT_TX_CLOCK_PARAM_NAME    "Port%u_InternalTxClock"   
+#define FS_SERIAL_INT_TX_CLOCK_PARAM_NAME_U  L"Port%u_InternalTxClock"
+
+#define FS_SERIAL_INT_RX_CLOCK_DEF           FALSE
+#define FS_SERIAL_INT_RX_CLOCK_PARAM_NAME    "Port%u_InternalRxClock"   
+#define FS_SERIAL_INT_RX_CLOCK_PARAM_NAME_U  L"Port%u_InternalRxClock"
+
+#define FS_SERIAL_TERM_TX_CLOCK_DEF           FALSE
+#define FS_SERIAL_TERM_TX_CLOCK_PARAM_NAME    "Port%u_TerminalTxClock"   
+#define FS_SERIAL_TERM_TX_CLOCK_PARAM_NAME_U  L"Port%u_TerminalTxClock"
+
+#define FS_SERIAL_TERM_RX_CLOCK_DEF           FALSE
+#define FS_SERIAL_TERM_RX_CLOCK_PARAM_NAME    "Port%u_TerminalRxClock"   
+#define FS_SERIAL_TERM_RX_CLOCK_PARAM_NAME_U  L"Port%u_TerminalRxClock"
+
+#define FS_SERIAL_DCD_OUTPUT_DEF           FALSE
+#define FS_SERIAL_DCD_OUTPUT_PARAM_NAME    "Port%u_DCDOutput"   
+#define FS_SERIAL_DCD_OUTPUT_PARAM_NAME_U  L"Port%u_DCDOutput"
+
+#define FS_PORT_MSB_DEF              FALSE
+#define FS_PORT_TX_MSB_PARAM_NAME    "Port%u_TxMSB"   
+#define FS_PORT_TX_MSB_PARAM_NAME_U  L"Port%u_TxMSB"
+#define FS_PORT_RX_MSB_PARAM_NAME    "Port%u_RxMSB"   
+#define FS_PORT_RX_MSB_PARAM_NAME_U  L"Port%u_RxMSB"
+   
+#endif // __FSCFG_H_
diff --git a/lib/farsync/windows/sdci.h b/lib/farsync/windows/sdci.h
new file mode 100644
index 0000000..220da48
--- /dev/null
+++ b/lib/farsync/windows/sdci.h
@@ -0,0 +1,700 @@
+/*******************************************************************************
+*                                                                 
+* Program     : FarSync (generic)
+*                                                                 
+* File        : sdci.h
+*                                                                 
+* Description : This header file is based on the Equates and Structure Layouts 
+*               page of the SDCI section of the July '99 MSDN
+*                                                    
+* Modifications
+*
+* Version 2.1.0  01Mar01  WEB  Add QuickStart and GetLinkInterface
+* Version 2.2.0  18Jul01  WEB  Certification candidate
+* Version 2.2.1  07Aug01  JPG  Add FarSyncReadSignals
+* Version 2.2.2  03Sep01  WEB  Extend USERDPC definition to include indication
+*                              param instead of bReadIR
+*                22Oct01  MJD  Added Transparent Mode support - defined 
+*                              LinkOption_Transparent
+* Version 3.0.0  12Sep02  WEB  Add dma mode and cardinfoex support definitions
+* Version 3.1.0  07Nov02  WEB  Add interrupt handshake mode support definitions
+* Version 3.2.0  09Dec02  WEB  Add LinkOption_InvertRxClock
+*                              Add ResetStats IOCTL and extended InterfaceRecord
+*                              Complete CardInfoEx definition
+* Version 3.3.0  30Apr04  WEB  Extend CardInfoEx to include physical + IO address
+* Version 3.3.1  03Mar05  WEB  Removed SA_TxAbort which was previously incorrectly
+*                              named 
+* Version 4.0.1  03Mar05  WEB  Correct IOCTL_SDCI_xxx definitions. Now requires
+*                              CTL_CODE to be defined i.e winioctl.h (user-mode) or
+*                              wdm.h (kernel-mode) must be included before this file.
+*                              Add USERDPC_INDICATION_TX, FarSyncSetUserDpcEx,
+*                              IoctlCodeFarSyncSetPortConfig,
+*                              IoctlCodeFarSyncGetPortConfig,
+*                              IoctlCodeFarSyncSetSerialConfig,
+*                              IoctlCodeFarSyncGetSerialConfig
+*                              IoctlCodeFarSyncSetCTBusConfig &
+*                              IoctlCodeFarSyncGetCTBusConfig
+* Version 4.0.1.1 03Mar05 WEB  Update FS_XXX_CONFIG structures
+* Version 4.0.1.2 04Mar05 WEB  Update error counter explanations,
+*                              FarSync-specific error codes & further
+*                              rationalisations
+* Version 4.1.0.0 15Jun05 WEB  Add TE1 and additional T4E definitions
+*                              Add monitoring IOCTLs
+* Version 4.1.0.1 02Aug05 MJD  Added USERDPC_INDICATION_CLOCK_SWITCH_TO_PRIMARY
+* Version 4.1.0.2 09Aug05 MJD  Update FS_CLOCKING_STATUS to include uCTAInUse so
+*                              that apps can tell which CT Bus the hardware is 
+*                              using in slave mode, structure version now 2. 
+* Version 4.2.0   12Sep05 WEB  Add async and synth detection fields to 
+*                              FSCARDINFOEX
+*                              SA_RxFrameTooBig is now supported by M1P
+*                              Add FS_ERROR_INVALID_LENGTH definition
+*
+*******************************************************************************/
+
+#ifndef __SDCI_H_ 
+#define __SDCI_H_
+
+/*****************************************************************************/
+//
+// There are the IOCTL code values used to communicate with the SDCI driver.
+//
+/*****************************************************************************/
+
+#define IOCTL_SDCI_SetEvent                        CTL_CODE(0, (0x410 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_SetLinkCharacteristics          CTL_CODE(0, (0x420 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_SetV24OutputStatus              CTL_CODE(0, (0x430 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_TransmitFrame                   CTL_CODE(0, (0x440 >> 2), METHOD_IN_DIRECT,  FILE_ANY_ACCESS)
+#define IOCTL_SDCI_AbortTransmit                   CTL_CODE(0, (0x450 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_AbortReceiver                   CTL_CODE(0, (0x460 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_OffBoardLoad                    CTL_CODE(0, (0x470 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_GetV24Status                    CTL_CODE(0, (0x620 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_ReceiveFrame                    CTL_CODE(0, (0x630 >> 2), METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncReceiveFrame             CTL_CODE(0, (0x630 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_ReadInterfaceRecord             CTL_CODE(0, (0x640 >> 2), METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncReadInterfaceRecord      CTL_CODE(0, (0x640 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncReadInterfaceRecordEx    CTL_CODE(0, (0x650 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncSetLinkInterface         CTL_CODE(0, (0x710 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncSetUserDpc               CTL_CODE(0, (0x720 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncSetCardMode              CTL_CODE(0, (0x730 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncReadCardInfo             CTL_CODE(0, (0x740 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncQuickStart               CTL_CODE(0, (0x750 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncGetLinkInterface         CTL_CODE(0, (0x760 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncReadSignals              CTL_CODE(0, (0x770 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncSetDMAMode               CTL_CODE(0, (0x780 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncGetDMAMode               CTL_CODE(0, (0x790 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncReadCardInfoEx           CTL_CODE(0, (0x7a0 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncSetHandShakeMode         CTL_CODE(0, (0x7b0 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncGetHandShakeMode         CTL_CODE(0, (0x7c0 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncResetStats               CTL_CODE(0, (0x7d0 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncReadTE1Status            CTL_CODE(0, (0x7e0 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncSetUserDpcEx             CTL_CODE(0, (0x7f0 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncSetPortConfig            CTL_CODE(0, (0x810 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncGetPortConfig            CTL_CODE(0, (0x820 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncSetSerialConfig          CTL_CODE(0, (0x830 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncGetSerialConfig          CTL_CODE(0, (0x840 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncSetCTBusConfig           CTL_CODE(0, (0x850 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncGetCTBusConfig           CTL_CODE(0, (0x860 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncSetTE1Config             CTL_CODE(0, (0x870 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncGetTE1Config             CTL_CODE(0, (0x880 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncSetCTBusBackupConfig     CTL_CODE(0, (0x890 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncGetCTBusBackupConfig     CTL_CODE(0, (0x8a0 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncGetClockingStatus        CTL_CODE(0, (0x8b0 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncSetMonitoring            CTL_CODE(0, (0x8c0 >> 2), METHOD_BUFFERED,   FILE_ANY_ACCESS)
+#define IOCTL_SDCI_FarSyncGetMonitoringStatus      CTL_CODE(0, (0x8d0 >> 2), METHOD_NEITHER,    FILE_ANY_ACCESS)
+
+#define IoctlCodeSetEvent                       IOCTL_SDCI_SetEvent
+#define IoctlCodeSetLinkChar                    IOCTL_SDCI_SetLinkCharacteristics
+#define IoctlCodeSetV24                         IOCTL_SDCI_SetV24OutputStatus
+#define IoctlCodeTxFrame                        IOCTL_SDCI_TransmitFrame   
+#define IoctlCodeAbortTransmit                  IOCTL_SDCI_AbortTransmit
+#define IoctlCodeAbortReceiver                  IOCTL_SDCI_AbortReceiver
+#define IoctlCodeOffBoardLoad                   IOCTL_SDCI_OffBoardLoad
+#define IoctlCodeGetV24                         IOCTL_SDCI_GetV24Status
+#define IoctlCodeRxFrame                        IOCTL_SDCI_ReceiveFrame   
+#define IoctlCodeFarSyncRxFrame                 IOCTL_SDCI_FarSyncReceiveFrame
+#define IoctlCodeReadInterfaceRecord            IOCTL_SDCI_ReadInterfaceRecord
+#define IoctlCodeFarSyncReadInterfaceRecord     IOCTL_SDCI_FarSyncReadInterfaceRecord
+#define IoctlCodeFarSyncReadInterfaceRecordEx   IOCTL_SDCI_FarSyncReadInterfaceRecordEx
+#define IoctlCodeFarSyncSetLinkInterface        IOCTL_SDCI_FarSyncSetLinkInterface
+#define IoctlCodeSetLinkInterface               IoctlCodeFarSyncSetLinkInterface
+#define IoctlCodeFarSyncSetUserDpc              IOCTL_SDCI_FarSyncSetUserDpc
+#define IoctlCodeFarSyncSetCardMode             IOCTL_SDCI_FarSyncSetCardMode
+#define IoctlCodeFarSyncReadCardInfo            IOCTL_SDCI_FarSyncReadCardInfo
+#define IoctlCodeFarSyncQuickStart              IOCTL_SDCI_FarSyncQuickStart
+#define IoctlCodeFarSyncGetLinkInterface        IOCTL_SDCI_FarSyncGetLinkInterface
+#define IoctlCodeFarSyncReadSignals             IOCTL_SDCI_FarSyncReadSignals
+#define IoctlCodeFarSyncSetDMAMode              IOCTL_SDCI_FarSyncSetDMAMode
+#define IoctlCodeFarSyncGetDMAMode              IOCTL_SDCI_FarSyncGetDMAMode
+#define IoctlCodeFarSyncReadCardInfoEx          IOCTL_SDCI_FarSyncReadCardInfoEx
+#define IoctlCodeFarSyncSetHandShakeMode        IOCTL_SDCI_FarSyncSetHandShakeMode
+#define IoctlCodeFarSyncGetHandShakeMode        IOCTL_SDCI_FarSyncGetHandShakeMode
+#define IoctlCodeFarSyncResetStats              IOCTL_SDCI_FarSyncResetStats
+#define IoctlCodeFarSyncReadTE1Status           IOCTL_SDCI_FarSyncReadTE1Status
+#define IoctlCodeFarSyncSetUserDpcEx            IOCTL_SDCI_FarSyncSetUserDpcEx
+#define IoctlCodeFarSyncSetPortConfig           IOCTL_SDCI_FarSyncSetPortConfig
+#define IoctlCodeFarSyncGetPortConfig           IOCTL_SDCI_FarSyncGetPortConfig
+#define IoctlCodeFarSyncSetSerialConfig         IOCTL_SDCI_FarSyncSetSerialConfig
+#define IoctlCodeFarSyncGetSerialConfig         IOCTL_SDCI_FarSyncGetSerialConfig
+#define IoctlCodeFarSyncSetCTBusConfig          IOCTL_SDCI_FarSyncSetCTBusConfig
+#define IoctlCodeFarSyncGetCTBusConfig          IOCTL_SDCI_FarSyncGetCTBusConfig
+#define IoctlCodeFarSyncSetTE1Config            IOCTL_SDCI_FarSyncSetTE1Config
+#define IoctlCodeFarSyncGetTE1Config            IOCTL_SDCI_FarSyncGetTE1Config
+#define IoctlCodeFarSyncSetCTBusBackupConfig    IOCTL_SDCI_FarSyncSetCTBusBackupConfig
+#define IoctlCodeFarSyncGetCTBusBackupConfig    IOCTL_SDCI_FarSyncGetCTBusBackupConfig
+#define IoctlCodeFarSyncGetClockingStatus       IOCTL_SDCI_FarSyncGetClockingStatus
+#define IoctlCodeFarSyncSetMonitoring           IOCTL_SDCI_FarSyncSetMonitoring
+#define IoctlCodeFarSyncGetMonitoringStatus     IOCTL_SDCI_FarSyncGetMonitoringStatus
+
+/*****************************************************************************/
+/* Constants for the driver-specific IOCtl return codes.                     */
+/*****************************************************************************/
+#define CEDNODMA 0xff80     /* Warning (NO DMA!) from set link chrctrstcs    */
+/*****************************************************************************/
+/* Equates for the link options byte 1.                                      */
+/*****************************************************************************/
+#define CEL4WIRE 0x80
+#define CELNRZI  0x40
+#define CELPDPLX 0x20
+#define CELSDPLX 0x10
+#define CELCLOCK 0x08
+#define CELDSRS  0x04
+#define CELSTNBY 0x02
+#define CELDMA   0x01
+
+/*****************************************************************************/
+/* Equates for the driver set link characteristics byte 1.                   */
+/*****************************************************************************/
+#define CED4WIRE 0x80
+#define CEDNRZI  0x40
+#define CEDHDLC  0x20
+#define CEDFDPLX 0x10
+#define CEDCLOCK 0x08
+#define CEDDMA   0x04
+#define CEDRSTAT 0x02
+#define CEDCSTAT 0x01
+
+/* Nicer names for NT-style code */
+
+#define LinkOption_4Wire           CED4WIRE
+#define LinkOption_InvertRxClock   CEDDMA
+#define LinkOption_NRZI            CEDNRZI
+#define LinkOption_HDLC            CEDHDLC
+#define LinkOption_FullDuplex      CEDFDPLX
+#define LinkOption_InternalClock   CEDCLOCK
+#define LinkOption_DMA             CEDDMA
+#define LinkOption_ResetStatistics CEDRSTAT
+#define LinkOption_Transparent     CEDCSTAT
+
+/*****************************************************************************/
+/* Equates for the output V24 interface flags.                               */
+/*****************************************************************************/
+#define CED24RTS 0x01
+#define CED24DTR 0x02
+// #define CED24DRS 0x04- not used. 0x04 is instead used by DCD 
+// i.e. when configured as an output - see below
+#define CED24SLS 0x08
+#define CED24TST 0x10
+
+/* Nicer names for NT-style code */
+
+#define IR_OV24RTS  CED24RTS
+#define IR_OV24DTR  CED24DTR
+//#define IR_OV24DSRS CED24DRS
+#define IR_OV24SlSt CED24SLS
+#define IR_OV24Test CED24TST
+
+
+/*****************************************************************************/
+/* Equates for the input V24 interface flags.                                */
+/*****************************************************************************/
+#define CED24CTS 0x01
+#define CED24DSR 0x02
+#define CED24DCD 0x04
+#define CED24RI  0x08
+
+// CEDCR indicates the presense of a generic carrier i.e. independent of port type
+// e.g. DCD for V.25, CTS for X.21
+#define CEDCR  0x10
+
+ // Note: DCD can only be used as an output signal on a FarSync T4E
+ // and only then if a FarSyncSetSerialConfig has been previously
+ // issued for this port, with FsSerialConfig.uDCDOutput set to
+ // TRUE
+
+/* Nicer names for NT-style code */
+
+#define IR_IV24CTS  CED24CTS
+#define IR_IV24DSR  CED24DSR
+#define IR_IV24DCD  CED24DCD
+#define IR_IV24RI   CED24RI
+#define IR_IV24Test 0x10
+
+
+/*****************************************************************************/
+/* Structure for the device driver interface record.                         */
+/*****************************************************************************/
+
+#define CEDSTCRC  0         /* Frames received with incorrect CRC            */
+#define CEDSTOFL  1         /* Frames received longer than the maximum       */
+#define CEDSTUFL  2         /* Frames received less than 4 octets long       */
+#define CEDSTSPR  3         /* Frames received ending on a non-octet bndry   */
+#define CEDSTABT  4         /* Aborted frames received                       */
+#define CEDSTTXU  5         /* Transmitter interrupt underruns               */
+#define CEDSTRXO  6         /* Receiver    interrupt overruns                */
+#define CEDSTDCD  7         /* DCD (RLSD) lost during frame reception        */
+#define CEDSTCTS  8         /* CTS lost while transmitting                   */
+#define CEDSTDSR  9         /* DSR drops                                     */
+#define CEDSTHDW 10         /* Hardware failures - adapter errors            */
+
+#define CEDSTMAX 11
+
+#define SA_CRC_Error       CEDSTCRC
+#define SA_RxFrameTooBig   CEDSTOFL
+#define SA_RxFrameTooShort CEDSTUFL
+#define SA_Spare           CEDSTSPR
+#define SA_RxAbort         CEDSTABT
+#define SA_TxUnderrun      CEDSTTXU
+#define SA_RxOverrun       CEDSTRXO
+#define SA_DCDDrop         CEDSTDCD
+#define SA_CTSDrop         CEDSTCTS
+#define SA_DSRDrop         CEDSTDSR
+#define SA_HardwareError   CEDSTHDW
+
+// FarSync-specific counters mapped to existing SDCI definitions 
+#define SA_FramingError       SA_Spare
+#define SA_RxError            SA_HardwareError
+#define SA_BufferUnavailable  SA_DCDDrop
+#define SA_Parity             SA_CRC_Error
+
+#define SA_Max_Stat        CEDSTMAX
+
+// ****************************************************************************************************
+// FarSync supports the following counters. All other counter indices are not used by FarSync.
+
+// SA_CRC_Error       Sync & Async modes
+// SA_FramingError    Sync & Async modes
+// SA_RxOverrun       Sync & Async modes
+
+// SA_RxAbort         (Async) & (M1P Sync) modes only
+// SA_RxError         Sync mode only
+// SA_TxUnderrun      Sync mode only
+// SA_RxFrameTooShort M1P Sync mode only
+
+// SA_RxFrameTooBig   Async mode (fifo overflow) & M1P Sync
+
+//    Note that 
+//      1) Async mode is currently only supported on the T4U - it is an optional extra feature
+//      2) On a TxU an SA_RxError indicates a received abort OR a rx frame length error (too big OR too small)
+//      3) On an M1P an SA_RxError indicates a alternative type of RxO as reported via SA_RxOverrun
+// ****************************************************************************************************
+
+/*****************************************************************************/
+/* InterfaceRecord definition                                                */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeReadInterfaceRecord,                                           */
+/*   IoctlCodeFarSyncReadInterfaceRecord                                     */
+/*                                                                           */
+/*****************************************************************************/
+typedef struct _INTERFACE_RECORD
+{
+  int    RxFrameCount;   /* incremented after each frame rx'd */
+  int    TxMaxFrSizeNow; /* max available frame size av. now  */
+                         /* (changes after each Tx DevIoctl   */
+                         /* to DD or after Tx completed)      */
+  int    StatusCount;    /* How many status events have been  */
+                         /* triggered.                        */
+  UCHAR  V24In;          /* Last 'getv24 i/p' value got       */
+  UCHAR  V24Out;         /* Last 'setv24 o/p' value set       */
+
+/* The values for the indexes into the link statistics array of the */
+/* various types of statistic. */
+
+  int    StatusArray[SA_Max_Stat];
+
+} IR, * PIR;
+
+/*****************************************************************************/
+/* InterfaceRecordEx definition                                              */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncReadInterfaceRecordEx                                   */
+/*                                                                           */
+/*****************************************************************************/
+typedef struct _INTERFACE_RECORD_EX
+{
+  IR     InterfaceRecord;
+  int    StatusCount;    /* How many status events have been  */
+  ULONG  OpenedCount;
+  ULONG  TxRequestCount;
+  ULONG  TxCompleteCount;
+  ULONG  RxPostedCount;
+  ULONG  RxCompleteCount;
+} IREX, * PIREX;
+
+/*****************************************************************************/
+/* Set link characteristics parameter block definition                       */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeSetLinkChar                                                    */
+/*                                                                           */
+/*****************************************************************************/
+typedef struct  _SLPARMS
+{
+  int     SLFrameSize;            /* max frame size on link, should    */
+                                  /* include 2-byte CRC - max is 8K    */
+  LONG    SLDataRate;             /* not used by us - external clocks  */
+  UCHAR   SLOurAddress1;          /* ) e.g C1/FF or 00/00 or 01/03     */
+  UCHAR   SLOurAddress2;          /* )                                 */
+  UCHAR   SLLinkOptionsByte;      /* see documentation & LinkOption_*  */
+  UCHAR   SLSpare1;
+} SLPARMS, *PSLPARMS;
+
+/*****************************************************************************/
+/* Set link interface parameter block definition                             */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncSetLinkInterface,                                       */
+/*   IoctlCodeFarSyncGetLinkInterface                                        */
+/*                                                                           */
+/*****************************************************************************/
+#pragma pack(push, 4)     /* Note: sizeof(FsLinkIfParms) is expected to be 0x10 */
+typedef struct  _FSLINKIFPARMS
+{
+    HANDLE Context;       // context for completion routine - not used 
+    USHORT MaxFrameSize;  // maximum frame size - not used
+    USHORT Interface;     // line interface: 
+    ULONG  BaudRate;      // baud rate
+    UCHAR  Reserved;      // reserved
+} FSLINKIFPARMS, * PFSLINKIFPARMS;
+#pragma pack(pop)
+
+// USER DPC DEFINITIONS - KERNEL-MODE ONLY
+
+#define USERDPC_INDICATION_RX     0
+#define USERDPC_INDICATION_SIGNAL 1
+#define USERDPC_INDICATION_ERROR  2
+#define USERDPC_INDICATION_TX     3 /* indicates that the number of tx buffers 
+                                       in use by the card has changed - examine
+                                       *pUserDpcTxBuffersInUse for the current value */
+
+// FarSync T4E clock notifications
+#define USERDPC_INDICATION_CLOCK_RATE_CHANGED        FS_INDICATION_CLOCK_RATE_CHANGED
+#define USERDPC_INDICATION_CLOCK_OUT_OF_TOLERANCE1   FS_INDICATION_CLOCK_OUT_OF_TOLERANCE1
+#define USERDPC_INDICATION_CLOCK_IN_TOLERANCE1       FS_INDICATION_CLOCK_IN_TOLERANCE1
+#define USERDPC_INDICATION_CLOCK_SWITCH_TO_BACKUP    FS_INDICATION_CLOCK_SWITCH_TO_BACKUP
+#define USERDPC_INDICATION_CLOCK_OUT_OF_TOLERANCE2   FS_INDICATION_CLOCK_OUT_OF_TOLERANCE2
+#define USERDPC_INDICATION_CLOCK_IN_TOLERANCE2       FS_INDICATION_CLOCK_IN_TOLERANCE2
+#define USERDPC_INDICATION_CLOCK_SWITCH_TO_OSC       FS_INDICATION_CLOCK_SWITCH_TO_OSC
+#define USERDPC_INDICATION_CLOCK_SWITCH_TO_CTA       FS_INDICATION_CLOCK_SWITCH_TO_CTA
+#define USERDPC_INDICATION_CLOCK_SWITCH_TO_CTB       FS_INDICATION_CLOCK_SWITCH_TO_CTB
+#define USERDPC_INDICATION_CLOCK_SWITCH_TO_PRIMARY   FS_INDICATION_CLOCK_SWITCH_TO_PRIMARY
+
+// user DPC callback - kernel mode only
+typedef VOID (*USERDPC)(PVOID /* caller's handle*/, unsigned char /* indication */);  
+
+/*****************************************************************************/
+/* Set user dpc parameter block definition                                   */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncSetUserDpc      ,                                       */
+/*                                                                           */
+/*****************************************************************************/
+#pragma pack(push, 4)     
+typedef struct  _FSUSERDPCINFO
+{
+  USERDPC fUserDpc;      // callback address
+  PVOID   pUserDpcParam; // param to supply in callback
+} FSUSERDPCINFO, * PFSUSERDPCINFO;
+
+/*****************************************************************************/
+/* Extended set user dpc parameter block definition                          */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncSetUserDpcEx    ,                                       */
+/*                                                                           */
+/* If used, this structure must be allocated in NonPaged memory.             */
+/*                                                                           */
+/*****************************************************************************/
+typedef struct  _FSUSERDPCINFOEX
+{
+  FSUSERDPCINFO fUserDpcInfo;
+  long *        pUserDpcTxBuffersInUse; // ref to a SDCI client-owned var that is used to maintain the number of tx buffers
+                                        // currently in use by the card.
+} FSUSERDPCINFOEX, * PFSUSERDPCINFOEX;
+#pragma pack(pop)
+
+/*****************************************************************************/
+/* Card mode parameter block definition                                      */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncSetCardMode     ,                                       */
+/*                                                                           */
+/*****************************************************************************/
+#pragma pack(push, 4)     
+typedef struct  _FSCARDMODE
+{
+  BOOLEAN bIdentifyMode;
+} FSCARDMODE, * PFSCARDMODE;
+#pragma pack(pop)
+
+/*****************************************************************************/
+/* Card info parameter block definition                                      */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncReadCardInfo    ,                                       */
+/*                                                                           */
+/*****************************************************************************/
+#pragma pack(push, 4)     
+typedef struct  _FSCARDINFO
+{
+  #define FSCARDINFO_VERSION  1
+  #define SERIAL_NO_LENGTH    8
+
+  ULONG  uVersion;       // Version of this structure
+  USHORT uDeviceId;
+  USHORT uSubSystemId;
+  ULONG  uNumberOfPorts;
+  char   szSerialNo[SERIAL_NO_LENGTH+1];
+  ULONG  uMajorRevision;
+  ULONG  uMinorRevision;
+  ULONG  uBuildState;
+  ULONG  uCPUSpeed;
+  ULONG  uMode;
+} FSCARDINFO, * PFSCARDINFO;
+#pragma pack(pop)
+
+/*****************************************************************************/
+/* DMA mode parameter block definition                                       */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncSetDMAMode,                                             */   
+/*   IoctlCodeFarSyncGetDMAMode    ,                                         */
+/*                                                                           */
+/*****************************************************************************/
+#pragma pack(push, 4)     
+typedef struct  _FSDMAMODE
+{
+  #define FSDMAMODE_VERSION       1
+  #define FSDMAMODE_OFF           1
+  #define FSDMAMODE_ON            2
+  #define FSDMAMODE_INTERMEDIATE  3 // use for processing rxs via intermediate buffer
+
+  ULONG  uVersion;       // Version of this structure
+  USHORT uTxDMAMode;
+  USHORT uRxDMAMode;
+} FSDMAMODE, * PFSDMAMODE;
+#pragma pack(pop)
+
+/*****************************************************************************/
+/* Interrupt handshake mode parameter block definition                       */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncSetHandShakeMode,                                       */   
+/*   IoctlCodeFarSyncGetHandShakeMode                                        */
+/*                                                                           */
+/*****************************************************************************/
+#pragma pack(push, 4)     
+typedef struct  _FSHANDSHAKEMODE
+{
+  #define FSHANDSHAKEMODE_VERSION       1
+  #define FSHANDSHAKEMODE_2             2
+  #define FSHANDSHAKEMODE_3             3
+
+  ULONG  uVersion;       // Version of this structure
+  USHORT uMode;
+} FSHANDSHAKEMODE, * PFSHANDSHAKEMODE;
+#pragma pack(pop)
+
+/*****************************************************************************/
+/* Extended card info parameter block definition                             */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncReadCardInfoEx  ,                                       */
+/*                                                                           */
+/*****************************************************************************/
+#pragma pack(push, 4)     
+typedef struct  _FSCARDINFOEX
+{
+  #define FSCARDINFOEX_VERSION  2
+
+  ULONG  uVersion;           // Version of this structure
+
+  char   szDeviceName[32+8]; // Including aligned PADDING to allow for null-terminator
+  PVOID  w_memory;           // Virtual addresses of Adapter Resources
+  PVOID  w_controlSpace;     
+  PVOID  w_localCfg;         
+  PVOID  w_ioSpace;
+  ULONG  z_memory;           // Lengths of Adapter Resources
+  ULONG  z_controlSpace;     
+  ULONG  z_localCfg;         
+  ULONG  z_ioSpace;
+
+  ULONG  uHiVersion;  
+  ULONG  uLoVersion;
+
+  ULONG  uReservedA[30]; // these are reserved for FarSite's own use
+
+  PVOID  p_memory;       // physical address of window - T-Series cards 
+  PVOID  p_io;           // main IO address of card
+  ULONG  uExtendedClockingSupported; // are (T4E) clock synths available on the card?
+  ULONG  uAsyncSupported;  // does the card support async
+  ULONG  uReservedB[28];   // these are currently unused
+
+} FSCARDINFOEX, * PFSCARDINFOEX;
+#pragma pack(pop)
+
+/*****************************************************************************/
+/* Port config parameter block definition                                    */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncSetPortConfig,                                          */   
+/*   IoctlCodeFarSyncGetPortConfig                                           */
+/*                                                                           */
+/*****************************************************************************/
+#pragma pack(push, 4)     
+typedef struct  _FS_PORT_CONFIG
+{
+  #define FSPORTCONFIG_VERSION       2
+
+  ULONG  uVersion;              // Version of this structure
+  ULONG  uPortTxNumBuffers;     // 2,4,8,16,32,64,128
+  ULONG  uPortRxNumBuffers;     // 2,4,8,16,32,64,128
+	ULONG  uPortTxBufferLength;   // Min=2 Max=64*1024 Def= 8*1024
+	ULONG  uPortRxBufferLength;   // Min=2 Max=64*1024 Def= 8*1024
+  ULONG  uPortTxDMA;            // See fscfg.h for values i.e. FSDMAMODE_OFF=1, FSDMAMODE_ON=2
+  ULONG  uPortRxDMA;            // See fscfg.h for values i.e. FSDMAMODE_OFF=1, FSDMAMODE_ON=2
+  ULONG  uPortStartTxRx;        // See smcuser.h for values i.e. START_TX=1 | START_RX=2
+  ULONG  uPortClockSource;      // See smcuser.h for values i.e. FS_CLOCK_REFERENCE_xxx
+                                // Currently only supported on T4E
+  ULONG  uPortTxMSB;            // FALSE ==> LSB (Default)
+  ULONG  uPortRxMSB;            // FALSE ==> LSB (Default)
+  ULONG  uPortMaxTxsOutstanding;// read-only - indicates how many txs can be outstanding at a time
+  ULONG  uReserved[52];
+} FS_PORT_CONFIG, *PFS_PORT_CONFIG;
+#pragma pack(pop)
+
+/*****************************************************************************/
+/* Serial config parameter block definition                                  */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncSetSerialConfig,                                        */   
+/*   IoctlCodeFarSyncGetSerialConfig                                         */
+/*                                                                           */
+/*****************************************************************************/
+#pragma pack(push, 4)     
+typedef struct  _FS_SERIAL_CONFIG
+{
+  #define FSSERIALCONFIG_VERSION   2
+
+  ULONG  uVersion;              // Version of this structure
+  ULONG  uPortInterface;        // See fscfg.h for values e.g. FS_LINE_INTERFACE_X21
+  ULONG  uPortRate;
+  ULONG  uPortClocking;         // See fscfg.h for values e.g. FS_LINE_CLOCKING_INTERNAL
+	ULONG  uPortTransparentMode;  // HDLC=0 Transparent=1
+  ULONG  uPortInvertRxClock;    // TRUE(1) or FALSE(0)
+  ULONG  uPortEncoding;         // See fscfg for values i.e. FS_PORT_ENCODING_xxx
+                                // Currently only supported on M1P
+
+  // The following fields have been added in Version 2 of this structure and not be
+  // processed if uVersion = 1
+  ULONG  uExtendedClocking; // subsequent fields only used if this is TRUE
+  ULONG  uInternalTxClock;  
+  ULONG  uInternalRxClock;  
+  ULONG  uTerminalTxClock;  
+  ULONG  uTerminalRxClock;  
+  ULONG  uDCDOutput;        // TRUE => DCD is an output
+
+  ULONG  uEstimatedLineSpeed; // returned by FarSyncGetSerialConfig for T4E only
+
+  ULONG  uReserved[54];
+} FS_SERIAL_CONFIG, *PFS_SERIAL_CONFIG;
+#pragma pack(pop)
+
+/*****************************************************************************/
+/* CTBus config parameter block definition                                   */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncSetCTBusConfig                                          */   
+/*   IoctlCodeFarSyncGetCTBusConfig                                          */
+/*                                                                           */
+/*****************************************************************************/
+#pragma pack(push, 4)     
+typedef struct  _FS_CT_BUS_CONFIG
+{
+  #define FSCTBUSCONFIG_VERSION       2
+
+  ULONG  uVersion;     // Version of this structure
+  ULONG  uCTBusMode;   // See smcuser.h for values i.e. FS_CT_BUS_MODE_xxx
+  ULONG  uCTBusFeed;   // See smcuser.h for values i.e. FS_CT_BUS_FEED_xxx
+  ULONG  uFallback;    // TRUE=>auto switch if clock ref fails
+  ULONG  uReserved[60];
+} FS_CT_BUS_CONFIG, *PFS_CT_BUS_CONFIG;
+#pragma pack(pop)
+
+/*****************************************************************************/
+/* Clocking Status block definition                                          */
+/*                                                                           */
+/* For use with:                                                             */
+/*                                                                           */
+/*   IoctlCodeFarSyncGetClockingStatus                                       */
+/*                                                                           */
+/*****************************************************************************/
+#pragma pack(push, 4)     
+typedef struct  _FS_CLOCKING_STATUS
+{
+  #define FSCLOCKINGSTATUS_VERSION       2
+
+  ULONG  uVersion;               // Version of this structure
+  ULONG  uPrimaryClockStatus;    // 0=out-of-tolerance, 1=good
+  ULONG  uBackupClockStatus;     // 0=out-of-tolerance, 1=good
+  ULONG  uCurrentConfigReference; // See smcuser.h for values i.e. FS_CT_CONFIG_xxx
+  ULONG  uCTAStatus;             // 0=out-of-tolerance, 1=good
+  ULONG  uCTBStatus;             // 0=out-of-tolerance, 1=good
+  USHORT uCurrentStatusSummary;  // bit map status word describing clocking state/config
+                                 // see smcuser.h for bit definitions
+  USHORT uReserved1;
+  ULONG  uCTAInUse;              // 0=CTB, 1=CTA - shows which CT Bus the card
+                                 // has selected for the slave clock source
+  ULONG  uReserved2[15]; 
+} FS_CLOCKING_STATUS, *PFS_CLOCKING_STATUS;
+#pragma pack(pop)
+
+//######################################################################################################
+//
+// FarSync Error Return Codes
+//
+// These return codes will be passed back from the FarSync SDCI driver in the IoStatus.Status field of 
+// the IRP and (if the SDCI client is a user-mode app) will be passed through transparently to the app 
+// via GetLastError().
+//
+
+#define FS_ERROR_INVALID_INPUT_BUFFER_LENGTH  0xE0000001
+#define FS_ERROR_INVALID_OUTPUT_BUFFER_LENGTH 0xE0000002
+#define FS_ERROR_PRIMARY_IOCTL                0xE0000003
+#define FS_ERROR_CARD_NOT_STARTED             0xE0000004
+#define FS_ERROR_INVALID_CT_BUS_MODE          0xE0000005
+#define FS_ERROR_INVALID_CT_BUS_FEED          0xE0000006
+#define FS_ERROR_INVALID_IOCTL_FOR_PORTTYPE   0xE0000007
+#define FS_ERROR_INVALID_LENGTH               0xE0000008
+
+//######################################################################################################
+
+
+
+#endif /* __SDCI_H_ */
+
diff --git a/lib/farsync/windows/smcuser.h b/lib/farsync/windows/smcuser.h
new file mode 100644
index 0000000..063c775
--- /dev/null
+++ b/lib/farsync/windows/smcuser.h
@@ -0,0 +1,451 @@
+/*******************************************************************************
+*                                                                 
+* Program     : FARSYNC 
+*                                                                 
+* File        : smcuser.h
+*                                                                 
+* Description : This common header file defines constants used throughout FarSync e.g. in
+*
+*                 1) onboard software
+*                 2) PC driver (farsynct)
+*                 3) user-mode config apps
+*                 4) higher-level drivers (e.g. fswan)
+*
+* Modifications
+*
+* Version 2.0.0  18Jan01  WEB  Created
+* Version 2.2.0  18Jul01  WEB  Certification candidate
+*                22Oct01  MJD  Added Transparent Mode Support - moved number and
+*                              size of buffer definitions her from smc.h.
+*                19Nov02  MJD  Added X.21 Dual clock interface mode X21D - only
+*                              for T1U/T2U/T4U.
+*                28Nov02  MJD  Added NOCABLE interface mode - only for T1U/T2U/
+*                              T4U/T4P, used only by CDE when stopping a port.
+* Version 3.0.0  08Oct03  MJD  Added TE1 parameter constants
+* Version 3.0.1  10Nov03  MJD  Added tx/rxBufferMode constants for TE1.
+* Version 3.0.2  03Nov04  MJD  Added DSL #define's
+* Version 3.0.3  24Feb05  WEB  Add FS_CLOCK_SOURCE_xxx and FS_CT_BUS_xxx values
+* Version 4.1.0  15Jun05  WEB  Update TE1 typedefs
+* Version 4.1.1  24Jun05  WEB  Add T4E MkII defs
+* Version 4.1.2  30Jun05  MJD  Add FS_CT_BUS_FEED_FROM_OSCILLATOR define.
+*                              Only define FS_CLOCK_SOURCE_PORT_A/B/C/D when
+*                              T4EMKI defined (not available on T4EMKII).
+* Version 4.1.3  07Jul05  MJD  Add FS_CONFIG_IN_USE_XXX and FS_INDICATION_CLOCK_XXX
+*                              values for T4E MkII.
+* Version 4.1.4  08Jul05  MJD  Added define for ANNEX_TYPE_AB (SHDSL)
+* Version 4.1.5  14Jul05  WEB  Rationalise clock reference defines
+* Version 4.1.6  15Jul05  MJD  Added FS_CCS_MASK_XXX defines
+* Version 4.1.7  02Aug05  MJD  Added FS_INDICATION_CLOCK_SWITCH_TO_PRIMARY define
+*******************************************************************************/
+
+#ifndef SMCUSER_H
+#define SMCUSER_H
+
+#ifndef UINT8
+#define UINT8  unsigned char
+#define INT8   char
+#define INT32  long
+#define UINT16 unsigned short
+#define UINT32 unsigned long
+#endif
+
+#define MAX_PORTS 4       /* maximum ports on T4P - fixed don't change*/
+
+/* Interface Types  */
+
+#define AUTO       0
+#define V24        1
+#define X21        2
+#define V35        3
+#define X21D       4
+#define NOCABLE    5
+#define RS530_449  6
+
+/* Clock Sources  */
+
+#define INTCLK 1
+#define EXTCLK 0
+
+#define FS_CLOCK_REFERENCE_OSCILLATOR    0  
+#define FS_CLOCK_REFERENCE_PORT_A        1 
+#define FS_CLOCK_REFERENCE_PORT_B        2 
+#define FS_CLOCK_REFERENCE_PORT_C        3 
+#define FS_CLOCK_REFERENCE_PORT_D        4 
+#define FS_CLOCK_REFERENCE_CTBUS         5  /* note: this value does not differentiate between CTA or CTB */ 
+#define FS_CLOCK_REFERENCE_CT_A          6 
+#define FS_CLOCK_REFERENCE_CT_B          7 
+
+#define FS_CT_BUS_MODE_SLAVE          0  /* FarSync card will act as SLAVE to the CT_BUS */
+#define FS_CT_BUS_MODE_MASTER_A       1  /* FarSync card will act as MASTER to the CT_BUS_A */
+#define FS_CT_BUS_MODE_MASTER_B       2  /* FarSync card will act as MASTER to the CT_BUS_B */
+#define FS_CT_BUS_MODE_DEFAULT        FS_CT_BUS_MODE_SLAVE
+
+#define FS_CONFIG_IN_USE_PRIMARY     0     /* Primary clock reference is in use            */
+#define FS_CONFIG_IN_USE_BACKUP      1     /* Backup clock reference is in use             */
+#define FS_CONFIG_IN_USE_OSCILLATOR  2     /* Local oscillator clock reference is in use   */
+#define FS_CONFIG_IN_USE_DEFAULT     FS_CONFIG_IN_USE_PRIMARY
+
+// Indications to be signalled via the cardNotifications FIFO
+
+#define FS_INDICATION_CLOCK_RATE_CHANGED        0x0080 /* 2 LSB's denote port A, B, C or D */
+#define FS_INDICATION_CLOCK_OUT_OF_TOLERANCE1   0x0084
+#define FS_INDICATION_CLOCK_IN_TOLERANCE1       0x0088
+#define FS_INDICATION_CLOCK_SWITCH_TO_BACKUP    0x008c
+#define FS_INDICATION_CLOCK_OUT_OF_TOLERANCE2   0x0090
+#define FS_INDICATION_CLOCK_IN_TOLERANCE2       0x0094
+#define FS_INDICATION_CLOCK_SWITCH_TO_OSC       0x0098
+#define FS_INDICATION_CLOCK_SWITCH_TO_CTA       0x009c
+#define FS_INDICATION_CLOCK_SWITCH_TO_CTB       0x00a0
+#define FS_INDICATION_CLOCK_SWITCH_TO_PRIMARY   0x00a4
+
+// Bit masks for isolating fields in uCurrentStatusSummary
+
+#define FS_CSS_MASK_SLAVE_MASTER  0x0100 /* 0 = Slave, 1 = Master              */
+#define FS_CSS_MASK_CTA_CTB       0x0080 /* 0 = A, 1 = B                       */
+#define FS_CSS_MASK_MASTER_SOURCE 0x0070 /* 000=A, 001=B, 010=C, 011=D, 100=LO */
+#define FS_CSS_MASK_PORT_A_SOURCE 0x0008 /* 0 = CT, 1 = LO                     */
+#define FS_CSS_MASK_PORT_B_SOURCE 0x0004 /* 0 = CT, 1 = LO                     */
+#define FS_CSS_MASK_PORT_C_SOURCE 0x0002 /* 0 = CT, 1 = LO                     */
+#define FS_CSS_MASK_PORT_D_SOURCE 0x0001 /* 0 = CT, 1 = LO                     */
+
+/* Tx/Rx Start Parameters */
+
+#define START_TX 1
+#define START_RX 2
+#define START_TX_AND_RX (START_TX | START_RX)
+#define START_DEFAULT START_TX_AND_RX
+
+
+// constants for t1/e1 service unit config
+// =======================================
+//
+// dataRate
+// rate is in bps: 8k - 1536/2048k (t1/e1), though n*64k is more usual
+// e1: 0 - 1984k => framed (fractional), 2048k => unframed
+// for e1 framed, bandwidth is allocated from the ninth bit of the frame
+// sequentially
+// for e1 unframed all 256 bits in the frame are used for data
+// t1: 0 - 1536k => framed (fractional), no unframed mode in t1.
+//
+
+#define DATARATE_DEFAULT 64000L
+
+// Clocking
+// 
+
+#define CLOCKING_SLAVE  0
+#define CLOCKING_DEFAULT CLOCKING_SLAVE
+#define CLOCKING_MASTER 1
+
+// Framing
+// 
+
+#define FRAMING_E1      0
+#define FRAMING_DEFAULT FRAMING_E1
+#define FRAMING_J1      1 
+#define FRAMING_T1      2 
+
+// Structure
+// 
+
+#define STRUCTURE_UNFRAMED   0
+#define STRUCTURE_E1_DOUBLE  1
+#define STRUCTURE_E1_CRC4    2
+#define STRUCTURE_E1_DEFAULT STRUCTURE_E1_CRC4
+#define STRUCTURE_DEFAULT    STRUCTURE_E1_CRC4
+#define STRUCTURE_E1_CRC4M   3
+#define STRUCTURE_T1_4       4
+#define STRUCTURE_T1_12      5
+#define STRUCTURE_T1_24      6
+#define STRUCTURE_T1_DEFAULT STRUCTURE_T1_24
+#define STRUCTURE_T1_72      7
+
+// Interface
+// RJ48C is available for e1 and t1, BNC is only available for e1
+//
+
+#define INTERFACE_RJ48C   0
+#define INTERFACE_DEFAULT INTERFACE_RJ48C
+#define INTERFACE_BNC     1
+
+// Coding
+// hdb3 is the normal coding scheme for e1
+// b8zs is the normal coding scheme for t1, though ami is sometimes used
+//
+
+#define CODING_HDB3       0
+#define CODING_E1_DEFAULT CODING_HDB3
+#define CODING_DEFAULT    CODING_HDB3
+#define CODING_NRZ        1
+#define CODING_CMI        2
+#define CODING_CMI_HDB3   3
+#define CODING_CMI_B8ZS   4
+#define CODING_AMI        5
+#define CODING_AMI_ZCS    6
+#define CODING_B8ZS       7
+#define CODING_T1_DEFAULT CODING_B8ZS
+
+// Line Build Out - for long haul t1 > 655ft (200m). Use with EQUALIZER_LONG.
+// This parameter is ignored in e1 mode and t1/j1 short haul mode.
+//
+
+#define LBO_0dB     0
+#define LBO_DEFAULT LBO_0dB
+#define LBO_7dB5    1
+#define LBO_15dB    2
+#define LBO_22dB5   3
+
+// Range - for short haul t1 < 655ft (200m). Use with EQUALIZER_SHORT.
+// This parameter is ignored in e1 mode and t1/j1 long haul mode.
+//
+
+#define RANGE_0_133_FT   0
+#define RANGE_DEFAULT    RANGE_0_133_FT
+#define RANGE_0_40_M     RANGE_0_133_FT
+
+#define RANGE_133_266_FT 1
+#define RANGE_40_81_M    RANGE_133_266_FT
+
+#define RANGE_266_399_FT 2
+#define RANGE_81_122_M   RANGE_266_399_FT
+ 
+#define RANGE_399_533_FT 3
+#define RANGE_122_162_M  RANGE_399_533_FT
+
+#define RANGE_533_655_FT 4
+#define RANGE_162_200_M  RANGE_533_655_FT
+
+// Receive Equalizer
+// short haul -10dB
+// long  haul -43dB (E1), -36dB (T1)
+// only -36dB can be met with 1.2 silicon, requires equalizer parameter RAM
+// changes for 2.1 silicon
+//
+
+#define EQUALIZER_SHORT   0
+#define EQUALIZER_DEFAULT EQUALIZER_SHORT
+#define EQUALIZER_LONG    1
+
+// Loop Mode
+// Local Loop transmits normally and loops PCM data on the line side of the
+// framers.
+// Payload Loop receives normally and loops TS0-TS31 or TS1-31 (with TS0
+// regenerated by FALC-56) to line on the PCM side of the framers.
+// Remote Loop receives normally and loops line data after clock recovery
+// the optional Jitter Attenuation is currently not enabled.
+
+#define LOOP_NONE            0
+#define LOOP_DEFAULT LOOP_NONE
+#define LOOP_LOCAL           1
+#define LOOP_PAYLOAD_EXC_TS0 2
+#define LOOP_PAYLOAD_INC_TS0 3
+#define LOOP_REMOTE          4
+
+// Buffer Mode
+// buffer_none bypasses the elastic buffer
+// 
+
+#define BUFFER_2_FRAME 0
+#define BUFFER_DEFAULT BUFFER_2_FRAME
+#define BUFFER_1_FRAME 1
+#define BUFFER_96_BIT  2
+#define BUFFER_NONE    3
+
+//
+// Starting Timeslot (for fractional)
+// E1 range 1 to 31, T1/J1 range 0 to 23
+// Min/max values enforced by card. Actual speed may also be restricted if
+// starting timeslot is too late in the frame.
+// Parameter ignored in unchannelized mode
+//
+
+#define STARTING_DEFAULT 0
+
+//
+// LOS detection threshold
+// level 0 allows LOS to be detected with larger  signal levels
+// level 7 allows LOS to be detected with smaller signal levels
+// the recommended default setting is level 2 - which is selected
+// by the card if LOS_DEFAULT is configured
+//
+
+#define LOS_DEFAULT 0
+
+#define LOS_LEVEL_0 1
+#define LOS_LEVEL_1 2
+#define LOS_LEVEL_2 3
+#define LOS_LEVEL_3 4
+#define LOS_LEVEL_4 5
+#define LOS_LEVEL_5 6
+#define LOS_LEVEL_6 7
+#define LOS_LEVEL_7 8
+
+#define LOS_SHORT 0x20
+#define LOS_LONG  0x70
+
+//
+// Idle code for unused timeslots
+//
+
+#define IDLE_HDLC_FLAG 0x7e
+#define IDLE_CODE_DEFAULT IDLE_HDLC_FLAG
+
+#define TRANSPARENT_MODE_DEFAULT  FALSE
+#define ENABLE_IDLE_CODE_DEFAULT  FALSE
+
+// constants for dsl service unit config
+// =======================================
+
+//
+// dataRate (G.SHDSL)
+// rate is in bps: 192kbps (3B + 0Z) - 2312kbps (36B + 1Z)
+// in 8kbps steps, where B is 64kbps and Z is 8kbps
+//
+
+//
+// Terminal Type
+//
+
+#define TERMINAL_TYPE_REMOTE  0
+#define TERMINAL_TYPE_CENTRAL 1
+
+//
+// Test Mode
+//
+// For User Diagnostics:
+//
+// Analog Transparent Loop     - loops from transmit line driver output to
+//                               receive AGC input, bypassing the hybrid.
+// Analog Non-Transparent Loop - loops transmit DAC back to receive AGC,
+//                               bypassing transmit line driver and the hybrid.
+//
+// Others test modes are for Compliance Testing only
+//
+
+#define TEST_MODE_NONE                        0
+#define TEST_MODE_DEFAULT TEST_MODE_NONE
+
+#define TEST_MODE_ALTERNATING_SINGLE_PULSE    1
+#define TEST_MODE_ANALOG_TRANSPARENT_LOOP     4
+#define TEST_MODE_ANALOG_NON_TRANSPARENT_LOOP 8
+#define TEST_MODE_TRANSMIT_SC_SR              9
+#define TEST_MODE_TRANSMIT_TC_PAM_SCRONE      10
+#define TEST_MODE_LINE_DRIVER_NO_SIGNAL       11
+#define TEST_MODE_AGC_TO_LINE_DRIVER_LOOP     12
+
+#define TEST_MODE_LOOP_TDM_TO_LINE            16
+#define TEST_MODE_LOOP_PAYLOAD_TO_LINE        17
+//
+// Annex Type A (US) or B (EU)
+//
+
+#define ANNEX_TYPE_B 0
+#define ANNEX_TYPE_DEFAULT ANNEX_TYPE_B
+#define ANNEX_TYPE_A 1
+#define ANNEX_TYPE_AB 2
+
+
+/* Small Buffers are used only for diagnostics */
+
+#define NUM_SMALL_TX_BUFFER 2
+#define NUM_SMALL_RX_BUFFER 8
+
+#define LEN_SMALL_TX_BUFFER 256 /* max size is 8192             */
+#define LEN_SMALL_RX_BUFFER 256
+
+/* Large Buffers are used for SDMA data */
+
+// MAX_TX/RX_BUFFER determines, at compile time, the maximum number of 
+// descriptors (hence buffers) per port for transmitter and receiver. Host can
+// use any 2**N number of the descriptors between 1 and MAX_TX/RX_BUFFER, so
+// some descriptors may be unused. Number of Buffers * Size of Buffers <=
+// TX/RX_BUFFER_SPACE. Fewer buffers mean bigger buffers, more buffers mean
+// smaller buffers.
+
+#define MAX_TX_BUFFER 128
+#define MAX_RX_BUFFER 128
+
+// MAX_TX/RX_BUFFER_SPACE determines, at compile time, how much buffer space is
+// available per port for transmitter and receiver. Buffer space is subdivided
+// into 2**N buffers by host driver at runtime.
+// Host can allocate 1 - MAX_TX/RX_BUFFER buffers.
+// 0x10000 => 64KB for transmit, 64KB for receive; 4 ports => 512KB.
+// MAX_TX/RX_BUFFER must be a 2**N multiple (for easy logic anlyser trigger).
+
+#define TX_BUFFER_SPACE 0x10000
+#define RX_BUFFER_SPACE 0x10000
+
+/* Rx Descriptor bits */
+
+#define FS_RX_DESC_ERR   0x4000
+#define FS_RX_DESC_FRAM  0x2000
+#define FS_RX_DESC_OFLO  0x1000
+#define FS_RX_DESC_CRC   0x0800
+#define FS_RX_DESC_HBUF  0x0400
+#define FS_RX_DESC_ENP   0x0100
+
+#define FS_RX_DESC_FRAM_ENP  0x2100
+#define FS_RX_DESC_CRC_ENP   0x0900
+
+#define NO_OF_DMA_CHANNELS 2
+
+// The following structures require 2-byte packing.
+// This file is used in a number of different environments.
+// Windows SDCI applications should therefore include this file implicitly by explicitly 
+// including fscfg.h which enables the packing directive to be used. 
+
+#ifdef SMCUSER_PACKING
+
+#if (SMCUSER_PACKING==1)
+#pragma pack(push, 2)
+#endif
+
+typedef struct SU_CONFIG
+{
+  UINT32 dataRate;        // data rate in bps
+  UINT8  clocking;        // master or slave
+  UINT8  framing;         // E1, T1 or J1
+  UINT8  structure;       // E1: unframed, double frame, CRC4; T1: F4, F12, F24 or F72
+  UINT8  iface;           // RJ48C or BNC
+  UINT8  coding;          // HDB3 or B8ZS + some other less used codes
+  UINT8  lineBuildOut;    // 0, -7.5, -15, -22.5dB for t1 long haul only
+  UINT8  equalizer;       // short or long haul settings
+  UINT8  transparentMode; // FALSE (hdlc) or TRUE transparent data
+  UINT8  loopMode;        // various local, payload and remote loops for test
+  UINT8  range;           // 0-133, 133-266, 266-399, 399-533, 533-655ft for t1 short haul only
+  UINT8  txBufferMode;    // transmit elastic buffer depth: 0 (bypass), 96 bits, 1 frame or 2 frame
+  UINT8  rxBufferMode;    // receive elastic buffer depth:  0 (bypass), 96 bits, 1 frame or 2 frame
+  UINT8  startingTimeSlot;// startingTimeSlot: E1 1-31, T1/J1 0-23
+  UINT8  losThreshold;    // LOS Threshold: E1/T1/J1 0-7
+  UINT8  enableIdleCode;  // Enable idle code for unused timeslots: TRUE, FALSE
+  UINT8  idleCode;        // Idle code for unused timeslots: 0x00 - 0xff
+
+  UINT8 spare[44];        // adjust to keep structure size 64 bytes
+} FS_TE1_CONFIG, *PFS_TE1_CONFIG;
+
+typedef struct SU_STATUS
+{
+  UINT32  receiveBufferDelay;    // delay through receive bufffer time slots (0-63)
+  UINT32  framingErrorCounter;   // count of framing errors
+  UINT32  codeViolationCounter;  // count of code violations
+  UINT32  crcErrorCounter1;      // count of CRC errors
+  INT32   lineAttenuation;       // receive line attenuation in dB, -ve => unknown
+  BOOLEAN portStarted;           //
+  BOOLEAN lossOfSignal;          // LOS alarm
+  BOOLEAN receiveRemoteAlarm;    // RRA alarm
+  BOOLEAN alarmIndicationSignal; // AIS alarm
+
+  UINT8 spare[40];               // adjust to keep structure size 64 bytes
+} FS_TE1_STATUS, *PFS_TE1_STATUS;
+
+#if (SMCUSER_PACKING==1)
+#pragma pack(pop)
+#endif
+
+#else
+#pragma message("!!! *** SMCUSER_PACKING not defined. Note: Windows SDCI apps should  *** !!!")
+#pragma message("!!! *** not include smcuser.h directly, use fscfg.h instead          *** !!!")
+#endif 
+
+
+#endif