From 5cf52c74e9eb6bf8a82af4509ff3eb5106f928f9 Mon Sep 17 00:00:00 2001 From: "Matthias P. Braendli" Date: Tue, 4 Dec 2018 16:45:58 +0100 Subject: Rework GUI and DPDCE --- python/dpd.ini | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 python/dpd.ini (limited to 'python/dpd.ini') diff --git a/python/dpd.ini b/python/dpd.ini new file mode 100644 index 0000000..31d6140 --- /dev/null +++ b/python/dpd.ini @@ -0,0 +1,60 @@ +[remotecontrol] +telnet=1 +telnetport=2121 +zmqctrl=1 +zmqctrlendpoint=tcp://127.0.0.1:9400 + +[log] +syslog=0 +filelog=1 +filename=/tmp/dabmod.log + +[input] +transport=tcp +source=localhost:9200 + +[modulator] +gainmode=var +rate=8192000 + +# keep in mind that the DPDCE will set the digital gain through the RC! +digital_gain=0.001 + +[firfilter] +enabled=1 + +[poly] +enabled=1 +polycoeffile=dpd/poly.coef + +# How many threads to use for the predistorter. +# If not set, detect automatically. +#num_threads=2 + +[output] +# to prepare a file for the dpd/iq_file_server.py script, +# use output=file +output=uhd + +[fileoutput] +filename=dpd.iq + +[uhdoutput] +device= +master_clock_rate=32768000 +type=b200 +txgain=80 +channel=13C +refclk_source=internal +pps_source=none +behaviour_refclk_lock_lost=ignore +max_gps_holdover_time=600 +dpd_port=50055 +rxgain=15 + +[delaymanagement] +; Use synchronous=1 so that the USRP time is set. This works +; even in the absence of a reference clk and PPS +synchronous=1 +mutenotimestamps=1 +offset=4.0 -- cgit v1.2.3