From f6d73ae3ee5f2af8e865bda2e1dbcd6132e7c9c8 Mon Sep 17 00:00:00 2001
From: "Matthias P. Braendli" <matthias.braendli@mpb.li>
Date: Wed, 9 May 2018 17:16:28 +0200
Subject: Document CIC equaliser better

---
 doc/example.ini | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'doc')

diff --git a/doc/example.ini b/doc/example.ini
index ae5ed46..a4bfb4a 100644
--- a/doc/example.ini
+++ b/doc/example.ini
@@ -106,9 +106,10 @@ digital_gain=0.8
 rate=2048000
 
 ; (DEPRECATED) CIC equaliser for USRP1 and USRP2
+; These USRPs have an upsampler in FPGA that does not have a flat frequency
+; response. The CIC equaliser compensates this. This setting is specific to
+; the USRP1 and USRP2 devices.
 ; Set to 0 to disable CicEqualiser
-; when set to 400000000, an additional USRP2 check is enabled.
-; See DabModulator.cpp line 186
 ;dac_clk_rate=0
 
 ; The USRP1 does not have flexible clocking, you will need
-- 
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