From 705ae30e5f7cc2525627f338beef8c90a8678c2f Mon Sep 17 00:00:00 2001 From: "Matthias P. Braendli" Date: Wed, 27 Feb 2019 11:37:53 +0100 Subject: Refactor Lime output * master_clock_rate sets CGEN clock, not sample rate * set sample rate accordingly * support only interpolate 1 and 2 * add frequency, txgain and temperature to RC * improve error handling * fix signedness of LMS_SendStream() return value --- doc/example.ini | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'doc') diff --git a/doc/example.ini b/doc/example.ini index b94825c..5dd2846 100644 --- a/doc/example.ini +++ b/doc/example.ini @@ -154,7 +154,7 @@ enabled=0 polycoeffile=polyCoefs [output] -; choose output: possible values: uhd, file, zmq, soapysdr +; choose output: possible values: uhd, file, zmq, soapysdr, limesdr output=uhd [fileoutput] @@ -306,6 +306,23 @@ channel=13C ; Set to 0 to disable ;dpd_port=50055 +[limeoutput] +; Lime output directly runs against the LMS device driver. It does not support SFN nor predistortion. +device= +;master_clock_rate= + +; txgain range: 0 .. 100 +txgain=20 +tx_antenna=BAND1 +;lo_offset=2048000 +;frequency=234208000 +channel=13C + +; The LimeSDR contains a FIR filter in FPGA that can be used to filter the IQ signal. +; This is useful because it allows us to upsample in a very cheap way in software instead +; of using the FFT-based resampler. +upsample=1 + ; Used for running single-frequency networks [delaymanagement] ; Enable handling of timestamps for SFN -- cgit v1.2.3