From eefe0ff989243b5af65fc6af0448fa4578fc713e Mon Sep 17 00:00:00 2001
From: "Matthias P. Braendli" <matthias.braendli@mpb.li>
Date: Fri, 12 May 2017 11:25:39 +0200
Subject: Update DPD readme and add example

---
 dpd/README.md |  8 ++++++++
 dpd/dpd.ini   | 41 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)
 create mode 100644 dpd/dpd.ini

diff --git a/dpd/README.md b/dpd/README.md
index 828a483..96c4fb0 100644
--- a/dpd/README.md
+++ b/dpd/README.md
@@ -8,3 +8,11 @@ This folder contains work in progress for digital predistortion. It requires:
 - A feedback connection from the power amplifier output, at an appropriate power level for the B200.
   Usually this is done with a directional coupler.
 - ODR-DabMod with enabled dpd_port, and with a samplerate of 8192000 samples per second.
+- Synchronous=1 so that the USRP has the timestamping set properly.
+
+See dpd/dpd.ini for an example.
+
+TODO
+----
+
+Fix timestamps and test if frame data is valid.
diff --git a/dpd/dpd.ini b/dpd/dpd.ini
new file mode 100644
index 0000000..906827b
--- /dev/null
+++ b/dpd/dpd.ini
@@ -0,0 +1,41 @@
+[remotecontrol]
+telnet=1
+telnetport=2121
+
+[log]
+syslog=0
+filelog=0
+filename=/dev/stderr
+
+[input]
+transport=tcp
+source=localhost:9200
+
+[modulator]
+digital_gain=0.9
+rate=8192000
+
+[firfilter]
+enabled=0
+
+[output]
+output=uhd
+
+[uhdoutput]
+device=
+master_clock_rate=32768000
+type=b200
+txgain=50
+channel=13C
+refclk_source=internal
+pps_source=none
+behaviour_refclk_lock_lost=ignore
+max_gps_holdover_time=600
+dpd_port=50055
+
+[delaymanagement]
+; Use synchronous=1 so that the USRP time is set. This works
+; even in the absence of a reference clk and PPS
+synchronous=1
+mutenotimestamps=1
+offset=4.0
-- 
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