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authorMatthias P. Braendli <matthias.braendli@mpb.li>2018-12-04 10:18:33 +0100
committerMatthias P. Braendli <matthias.braendli@mpb.li>2018-12-04 10:18:33 +0100
commitd5cbe10c0e2298b0e40161607a3da158249bdb82 (patch)
tree5f6a0ff40ce5b3dd39d0df1c348557b183b48a7e /python/dpd/dpd.ini
parent594cb2691debaa7562fd7d76d3b224701ec087ea (diff)
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Move python stuff to folder
Diffstat (limited to 'python/dpd/dpd.ini')
-rw-r--r--python/dpd/dpd.ini60
1 files changed, 60 insertions, 0 deletions
diff --git a/python/dpd/dpd.ini b/python/dpd/dpd.ini
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+[remotecontrol]
+telnet=1
+telnetport=2121
+zmqctrl=1
+zmqctrlendpoint=tcp://127.0.0.1:9400
+
+[log]
+syslog=0
+filelog=1
+filename=/tmp/dabmod.log
+
+[input]
+transport=tcp
+source=localhost:9200
+
+[modulator]
+gainmode=var
+rate=8192000
+
+# keep in mind that the DPDCE will set the digital gain through the RC!
+digital_gain=0.001
+
+[firfilter]
+enabled=1
+
+[poly]
+enabled=1
+polycoeffile=dpd/poly.coef
+
+# How many threads to use for the predistorter.
+# If not set, detect automatically.
+#num_threads=2
+
+[output]
+# to prepare a file for the dpd/iq_file_server.py script,
+# use output=file
+output=uhd
+
+[fileoutput]
+filename=dpd.iq
+
+[uhdoutput]
+device=
+master_clock_rate=32768000
+type=b200
+txgain=80
+channel=13C
+refclk_source=internal
+pps_source=none
+behaviour_refclk_lock_lost=ignore
+max_gps_holdover_time=600
+dpd_port=50055
+rxgain=15
+
+[delaymanagement]
+; Use synchronous=1 so that the USRP time is set. This works
+; even in the absence of a reference clk and PPS
+synchronous=1
+mutenotimestamps=1
+offset=4.0