Wed Oct 28 18:49:28 2015
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author
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0
center_freq25
0
norm_gain25
False
gain25
0
ant26
bw26
0
center_freq26
0
norm_gain26
False
gain26
0
ant27
bw27
0
center_freq27
0
norm_gain27
False
gain27
0
ant28
bw28
0
center_freq28
0
norm_gain28
False
gain28
0
ant29
bw29
0
center_freq29
0
norm_gain29
False
gain29
0
ant2
bw2
0
center_freq2
0
norm_gain2
False
gain2
0
ant30
bw30
0
center_freq30
0
norm_gain30
False
gain30
0
ant31
bw31
0
center_freq31
0
norm_gain31
False
gain31
0
ant3
bw3
0
center_freq3
0
norm_gain3
False
gain3
0
ant4
bw4
0
center_freq4
0
norm_gain4
False
gain4
0
ant5
bw5
0
center_freq5
0
norm_gain5
False
gain5
0
ant6
bw6
0
center_freq6
0
norm_gain6
False
gain6
0
ant7
bw7
0
center_freq7
0
norm_gain7
False
gain7
0
ant8
bw8
0
center_freq8
0
norm_gain8
False
gain8
0
ant9
bw9
0
center_freq9
0
norm_gain9
False
gain9
0
clock_rate
0.0
comment
affinity
dev_addr
""
dev_args
""
_enabled
True
_coordinate
(1312, 263)
_rotation
0
id
uhd_usrp_sink_0
type
fc32
clock_source0
sd_spec0
time_source0
clock_source1
sd_spec1
time_source1
clock_source2
sd_spec2
time_source2
clock_source3
sd_spec3
time_source3
clock_source4
sd_spec4
time_source4
clock_source5
sd_spec5
time_source5
clock_source6
sd_spec6
time_source6
clock_source7
sd_spec7
time_source7
nchan
1
num_mboards
1
samp_rate
samp_rate
hide_cmd_port
False
stream_args
stream_chans
[]
sync
len_tag_name
otw
uhd_usrp_source
alias
ant0
bw0
0
center_freq0
freq
dc_offs_enb0
""
iq_imbal_enb0
""
norm_gain0
False
gain0
rxgain
ant10
bw10
0
center_freq10
0
dc_offs_enb10
""
iq_imbal_enb10
""
norm_gain10
False
gain10
0
ant11
bw11
0
center_freq11
0
dc_offs_enb11
""
iq_imbal_enb11
""
norm_gain11
False
gain11
0
ant12
bw12
0
center_freq12
0
dc_offs_enb12
""
iq_imbal_enb12
""
norm_gain12
False
gain12
0
ant13
bw13
0
center_freq13
0
dc_offs_enb13
""
iq_imbal_enb13
""
norm_gain13
False
gain13
0
ant14
bw14
0
center_freq14
0
dc_offs_enb14
""
iq_imbal_enb14
""
norm_gain14
False
gain14
0
ant15
bw15
0
center_freq15
0
dc_offs_enb15
""
iq_imbal_enb15
""
norm_gain15
False
gain15
0
ant16
bw16
0
center_freq16
0
dc_offs_enb16
""
iq_imbal_enb16
""
norm_gain16
False
gain16
0
ant17
bw17
0
center_freq17
0
dc_offs_enb17
""
iq_imbal_enb17
""
norm_gain17
False
gain17
0
ant18
bw18
0
center_freq18
0
dc_offs_enb18
""
iq_imbal_enb18
""
norm_gain18
False
gain18
0
ant19
bw19
0
center_freq19
0
dc_offs_enb19
""
iq_imbal_enb19
""
norm_gain19
False
gain19
0
ant1
bw1
0
center_freq1
0
dc_offs_enb1
""
iq_imbal_enb1
""
norm_gain1
False
gain1
0
ant20
bw20
0
center_freq20
0
dc_offs_enb20
""
iq_imbal_enb20
""
norm_gain20
False
gain20
0
ant21
bw21
0
center_freq21
0
dc_offs_enb21
""
iq_imbal_enb21
""
norm_gain21
False
gain21
0
ant22
bw22
0
center_freq22
0
dc_offs_enb22
""
iq_imbal_enb22
""
norm_gain22
False
gain22
0
ant23
bw23
0
center_freq23
0
dc_offs_enb23
""
iq_imbal_enb23
""
norm_gain23
False
gain23
0
ant24
bw24
0
center_freq24
0
dc_offs_enb24
""
iq_imbal_enb24
""
norm_gain24
False
gain24
0
ant25
bw25
0
center_freq25
0
dc_offs_enb25
""
iq_imbal_enb25
""
norm_gain25
False
gain25
0
ant26
bw26
0
center_freq26
0
dc_offs_enb26
""
iq_imbal_enb26
""
norm_gain26
False
gain26
0
ant27
bw27
0
center_freq27
0
dc_offs_enb27
""
iq_imbal_enb27
""
norm_gain27
False
gain27
0
ant28
bw28
0
center_freq28
0
dc_offs_enb28
""
iq_imbal_enb28
""
norm_gain28
False
gain28
0
ant29
bw29
0
center_freq29
0
dc_offs_enb29
""
iq_imbal_enb29
""
norm_gain29
False
gain29
0
ant2
bw2
0
center_freq2
0
dc_offs_enb2
""
iq_imbal_enb2
""
norm_gain2
False
gain2
0
ant30
bw30
0
center_freq30
0
dc_offs_enb30
""
iq_imbal_enb30
""
norm_gain30
False
gain30
0
ant31
bw31
0
center_freq31
0
dc_offs_enb31
""
iq_imbal_enb31
""
norm_gain31
False
gain31
0
ant3
bw3
0
center_freq3
0
dc_offs_enb3
""
iq_imbal_enb3
""
norm_gain3
False
gain3
0
ant4
bw4
0
center_freq4
0
dc_offs_enb4
""
iq_imbal_enb4
""
norm_gain4
False
gain4
0
ant5
bw5
0
center_freq5
0
dc_offs_enb5
""
iq_imbal_enb5
""
norm_gain5
False
gain5
0
ant6
bw6
0
center_freq6
0
dc_offs_enb6
""
iq_imbal_enb6
""
norm_gain6
False
gain6
0
ant7
bw7
0
center_freq7
0
dc_offs_enb7
""
iq_imbal_enb7
""
norm_gain7
False
gain7
0
ant8
bw8
0
center_freq8
0
dc_offs_enb8
""
iq_imbal_enb8
""
norm_gain8
False
gain8
0
ant9
bw9
0
center_freq9
0
dc_offs_enb9
""
iq_imbal_enb9
""
norm_gain9
False
gain9
0
clock_rate
0.0
comment
affinity
dev_addr
""
dev_args
""
_enabled
1
_coordinate
(640, 342)
_rotation
0
id
uhd_usrp_source_0
maxoutbuf
0
clock_source0
sd_spec0
time_source0
clock_source1
sd_spec1
time_source1
clock_source2
sd_spec2
time_source2
clock_source3
sd_spec3
time_source3
clock_source4
sd_spec4
time_source4
clock_source5
sd_spec5
time_source5
clock_source6
sd_spec6
time_source6
clock_source7
sd_spec7
time_source7
minoutbuf
0
nchan
1
num_mboards
1
type
fc32
samp_rate
samp_rate
hide_cmd_port
False
stream_args
stream_chans
[]
sync
otw
analog_sig_source_x_0
blocks_add_xx_0
0
1
analog_sig_source_x_1
blocks_add_xx_0
0
0
blocks_add_xx_0
blocks_multiply_const_vxx_1
0
0
blocks_add_xx_1
qtgui_freq_sink_x_0_0_0
0
0
blocks_add_xx_1
qtgui_time_sink_x_0
0
0
blocks_add_xx_1
qtgui_time_sink_x_1
0
0
blocks_add_xx_1
uhd_usrp_sink_0
0
0
blocks_complex_to_real_0
qtgui_time_sink_x_0_0
0
0
blocks_file_source_0
blocks_multiply_const_vxx_1
0
0
blocks_file_source_0_0
blocks_multiply_const_vxx_1
0
0
blocks_message_burst_source_0
blocks_null_sink_0_2
0
0
blocks_multiply_const_vxx_0
blocks_add_xx_1
0
1
blocks_multiply_const_vxx_1
blocks_multiply_const_vxx_2
0
0
blocks_multiply_const_vxx_1
dpd_lut_0
0
0
blocks_multiply_const_vxx_2
blocks_add_xx_1
0
0
dpd_lut_0
blocks_multiply_const_vxx_0
0
0
uhd_amsg_source_0
blocks_message_burst_source_0
msg
msg
uhd_usrp_source_0
blocks_complex_to_real_0
0
0
uhd_usrp_source_0
blocks_null_sink_0_2_0
0
0
uhd_usrp_source_0
qtgui_const_sink_x_0
0
0
uhd_usrp_source_0
qtgui_freq_sink_x_0_0
0
0