| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Connect ATTiny and PLL differently | Matthias P. Braendli | 2022-04-09 | 1 | -2562/+994 |
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| * | Place and route | Matthias P. Braendli | 2022-04-08 | 1 | -1/+20202 |
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| * | Start schematic | Matthias P. Braendli | 2022-04-08 | 1 | -0/+2 |
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index : ADF4002_27MHz_PLL | |
| A PLL around the ADF4002 to generate 27MHz from a 10MHz ref |
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